Claims
- 1. A memory device comprising:
a plurality of memory cells arranged in a row and columns, in NOR configuration, each one of the plurality of memory cells being configured to accept a data bit at a programming input in the presence of an enable voltage at a program enable input, and being configured to store the bit of data as one of a plurality of logic levels, the memory cells including a first group of memory cells; a plurality of bit registers for storing data bits to be programmed in the memory cells of the first group; a program voltage generator having an output at which is supplied a program voltage for programming the memory cells; connection means for selectively connecting the output of the program voltage generator to the programming inputs of the memory cells of the first group according to the data bits stored in the bit registers, such that only those memory cells of the first group that require programming according to the data bits stored in the bit registers are connected to the program voltage generator.
- 2. The device according to claim 1 wherein the plurality of memory cells includes a second group of memory cells arranged in a different row than the first group, wherein the connecting means are configured to connect the program voltage generator to the cells of the first and second groups simultaneously.
- 3. The device according to claim 2 wherein the connection means are addressable and are configured to connect the plurality of bit registers to the programming input of each of the memory cells of the first group, or to the programming input of each of the memory cells of the second group.
- 4. The device of claim 1 wherein the plurality of bit registers is a first group of bits registers, the device further comprising:
a second group of bit registers; and means for sequentially storing a plurality of data bit groups in the first and second groups of bit registers, respectively.
- 5. The device of claim 1, further comprising:
timing means for supplying a read enable signal to a first enable input of the plurality of bit registers, sequentially, to enable each one of the plurality of bit registers to receive a successive one of the stream of data bits; and enabling means for providing a write enable signal at a second enable input of each of the plurality of bit registers simultaneously, and further, for concurrently providing the enable voltage at the program enable input of each of the plurality of memory cells.
- 6. A device for programming a memory array, comprising:
a circuit configured to receive a plurality of data words, address a plurality of memory cells equal to a total number of bits in the plurality of words, and enable writing to a respective one of the plurality of memory cells for each bit, of the total number of bits, that has a first logic level; and a program voltage generator configured to simultaneously program each of the write enabled memory cells at a voltage corresponding to the first logic level.
- 7. The device of claim 6, further comprising a circuit configured to pre-program each of the plurality of memory cells at a voltage corresponding to a second logic level.
- 8. The device of claim 6 wherein each of the plurality of data words is on a different row of the memory array.
- 9. The device of claim 6 wherein the circuit is further configured to receive a single data word, address a plurality of memory cells equal to a total number of bits in the single word, and enable writing to a respective one of the plurality of memory cells for each bit, of the ingle word, that has a first logic level.
- 10. The device of claim 6 wherein:
The circuit is further configured to receive an additional plurality of data words; the circuit is further configured to address an additional plurality of memory cells equal to the total number of bits in the additional plurality of words, and enable writing to a respective one of the additional plurality of memory cells for each bit, of the total number of bits in the additional plurality of words, that has a first logic level; and wherein the program voltage generator is further configured to simultaneously program each of the write enabled memory cells, of the additional plurality of cells, at a voltage corresponding to the first logic level.
- 11. A memory device, comprising:
means for a receiving a plurality of data words, address a plurality of memory cells equal to a total number of bits in the plurality of words, and enable writing to a respective one of the plurality of memory cells for each bit, of the total number of bits, that has a first logic level; and means for programming each of the write enabled memory cells at a voltage corresponding to the first logic level.
- 12. The device of claim 11, further comprising means for pre-programming each of the plurality of memory cells at a voltage corresponding to a second logic level.
Priority Claims (1)
Number |
Date |
Country |
Kind |
00830209.3 |
Mar 2000 |
EP |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application No. 09/817,363 (U.S. Pat. No. 6,414,875), filed Mar. 20, 2001, now issued, and U.S. patent application Ser. No. 10/179,553, filed Jun. 24, 2002, now pending, which applications are incorporated herein by reference in their entireties.
Divisions (2)
|
Number |
Date |
Country |
Parent |
10179553 |
Jun 2002 |
US |
Child |
10742429 |
Dec 2003 |
US |
Parent |
09817363 |
Mar 2001 |
US |
Child |
10179553 |
Jun 2002 |
US |