Structure for a Method and Structure for Screening NFET-to-PFET Device Performance Offsets Within a CMOS Process

Abstract

A design structure of a method of screening on-chip variation in NFET-to-PFET device performance for as-manufactured integrated circuits (ICs) made using a CMOS process. The method includes defining an acceptable frequency- or period-NFET-to-PFET device performance envelope by simulating a pair of ring oscillators, one of which contains only NFET transistors and the other of which contains only PFET transistors. The ring oscillators are then fabricated into each as-manufactured ICs. At screening time, the ring oscillators in each fabricated IC are tested to measure their frequencies (periods). These frequencies (periods) are then compared to the performance envelope to determine whether the NFET-to-PFET device performance of the corresponding IC is acceptable or not.

Description

FIELD OF THE INVENTION

The present invention generally relates to the field of quality control for CMOS integrated circuits. In particular, the present invention is directed to a design structure for a method and structure for screening NFET-to-PFET device performance offsets within a CMOS process.

BACKGROUND

In prior generations of complementary metallic oxide semiconductor (CMOS) technology, shipped product quality level (SPQL) exposure was generally controlled using statistical analyses of chip-to-chip, wafer-to-wafer and lot-to-lot variations resulting from variations in the steps of the process used to fabricate the integrated circuits (ICs). However, as feature size continues to shrink to 90 nm and below with advancing CMOS technologies, across-chip variations in features such as transistor channel length are increasingly affecting SPQL exposure.

One variation of interest in CMOS technology is the performance offset variation between p-type and n-type field effect transistors (PFETs and NFETs, respectively). A parameter often used in conventional PFET-to-NFET device performance analysis is the saturation current of the PFETs and NFETs. During Monte Carlo simulation of the saturation currents (Ion) of a PFET and a corresponding NFET, a scattergram (such as scattergram 100 of FIG. 1) is typically obtained, as are statistics, such as the normalized distribution 200 of FIG. 2. Designers can then use this and other statistical information in performing their circuit analyses.

For example and referring again to FIG. 1, statistics calculated for the PFET and NFET saturation currents can be used to define a set of test screening boundaries 104, here plus and minus three standard deviations (±3 σ), that define an acceptable performance envelope 108 that sets the upper and lower bounds on acceptable PFET-to-NFET Ion performance offset. Designers would then use test screening limit boundaries 104 (i.e., the ±3 σ values) during testing of as-manufactured ICs to screen-out ICs having PFET-to-NFET device performance mismatch that falls outside acceptable performance envelope 108. Fabricated ICs having actual PFET-to-NFET Ion performance at, for example, points 112 outside acceptable performance envelope 108 would not be shipped, whereas chips having actual PFET-to-NFET Ion performance at points such as points 116 within the acceptable performance envelope would be shipped (assuming other screening measures are satisfied).

SUMMARY OF THE DISCLOSURE

In one implementation, the present disclosure is directed to a design structure embodied in a machine readable medium. The design structure includes: a CMOS layout that includes: a plurality of PFETs; a plurality of NFETs; a first ring oscillator in which all transistors therein are ones of the plurality of PFETs, the first ring oscillator having a first frequency; and a second ring oscillator in which all transistors therein are ones of the plurality of NFETs, the second ring oscillator having a second frequency; and a plurality of test points in communication with the first and second ring oscillators so as to permit measurement of the first and second frequencies.

BRIEF DESCRIPTION OF THE DRAWINGS

For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention. However, it should be understood that the present invention is not limited to the precise arrangements and instrumentalities shown in the drawings, wherein:

FIG. 1 is a prior art scattergram of PFET saturation current versus NFET saturation current showing variation in saturation current resulting from variation in a CMOS fabrication process and showing conventional test screening limit boundaries used in screening as fabricated circuit;

FIG. 2 is a prior art statistical distribution of NFET-to-PFET saturation current offset normalized to nominal;

FIG. 3 is a scattergram of PFET saturation current versus NFET saturation current illustrating additional screening limit boundaries that would be desirable to reduce shipped product quality level (SPQL) exposure of CMOS-based integrated circuits;

FIG. 4 is a flow diagram of a screening method in accordance with the present invention of reducing SPQL exposure CMOS-based integrated circuits;

FIG. 5 is a schematic diagram of a pair of NFET and PFET ring oscillators that may be used in performing a method of the present invention;

FIG. 6 is a high-level diagram of an exemplary physical layout of an integrated circuit containing the NFET and PFET ring oscillators of FIG. 5;

FIG. 7A is a schematic diagram of a bootstrap NFET inverter that may be used in the NFET ring oscillator of FIGS. 5 and 6; FIG. 7B is a schematic diagram of a bootstrap PFET inverter that may be used in the PFET ring oscillator of FIGS. 5 and 6;

FIG. 8 is a scattergram of PFET period versus NFET period for a pair of complementary PFET and NFET ring oscillator designs showing enhanced test screening limit boundaries that include upper and lower ratio screen limit boundaries that can be determined using a screening method of the present invention; and

FIG. 9 is a flow diagram of a design process used in semiconductor design, manufacturing, and/or test.

DETAILED DESCRIPTION

The present invention is directed to a design structure for a method and structure for screening NFET-to-PFET device performance offsets within a CMOS process. FIG. 3 contains a diagram 300 illustrating the same scattergram 100 and test screening limit boundaries 104 shown in FIG. 1, as well as an additional set of boundaries 308 and 312 that take advantage of inherent NFET to PFET performance tracking envelope 108. This tracking is a result of many common process steps that NFETs and PFETs share (e.g. trench isolation, gate oxide growth, polysilcon deposition and etch, etc.) which in turn reduces the probability of NFET to PFET performance offsets within regions 302 and 304. Having a circuit characterization methodology that takes advantage of this tracking will result in faster circuits, which in turn results in higher performance systems at little or no extract cost. While test screening boundaries 104, here ±3 σ values of each of PFET and NFET saturation currents (Ion), allow quality control to provide a certain shipped product quality level (SPQL), it has been recognized that potential SPQL exposure exists for PFET-to-NFET device performance mismatch having tested points falling within potential SPQL exposure regions 302, 304 that are within acceptable performance envelope 108. Therefore, it would be desirable to be able to establish additional test screening boundaries, such as boundaries 308, 312, that define the extent of potential SPQL exposure regions 302, 304. Unfortunately, it is difficult to measure saturation currents of as-fabricated NFETs and PFETs, making a screening process using boundaries 308, 312 impractical to implement.

The present inventor has found, however, that instead of using saturation current as the parameter of interest in a PFET-to-NFET performance offset screening process, such performance screening can be implemented using unique ring oscillators and focusing on the frequency (period) of each ring oscillator as the parameter of interest. As will be seen below, test screening limit boundaries similar to test screening limit boundaries 308, 312 based on frequency (period) can be established, and fabricated integrated circuits (ICs) containing instantiations of the ring oscillators can be readily tested to measure their frequencies (periods). Novel screening structures for implementing these novel methods are described in detail below. It is noted that the pertinent steps of any method of the present disclosure are equally applicable to frequency and period, since each is simply the inverse of the other. Therefore, for example, despite the fact that the appended claims use only the terms “frequency” and “frequencies,” it will be apparent to the reader that the terms “period” and “periods” can be substituted therefore, since any measurement of frequency will inherently yield a measurement of period.

FIG. 4 illustrates an exemplary screening method 400 of the present invention for use in screening as-manufactured CMOS-based ICs based on PFET-to-NFET device performance offset values. At step 405, a designer lays out two ring oscillator designs, a first ring oscillator design in which all of the transistors are only PFETs and a complementary second ring oscillator design in which all of the transistors are only NFETs. As will be described below, these ring oscillator designs will be used at two stages of screening method 400, first, at a modeling stage to develop test screening limit boundaries to be used in screening as-fabricated ICs and, second, at a fabrication stage in which the designs will be instantiated into fabricated ICs. During screening, the instantiated ring oscillators will be tested to measure their frequencies, which will be compared to the test screening limit boundaries to determine whether or not the corresponding respective ICs meet the NFET-to-PFET performance offset criteria.

FIG. 5 illustrates an NFET-only ring oscillator design 500 and a complementary PFET-only ring oscillator design 504 that may be used for the first and second ring oscillator designs for use in a screening method of the present invention, such as screening method 400. As readily seen in FIG. 5, each ring oscillator design 500, 504 is made up of a series of inverters 508, 512, much like conventional ring oscillators. However, a unique feature of ring oscillator designs 500, 504 is that all of the transistors (not shown, but see, e.g., FIG. 8A) of NFET-only oscillator design 500 are NFETs and all of the transistors (not shown, but see, e.g., FIG. 8B) of PFET-only oscillator design 504 are PFETs. By “complementary,” it is meant that other aspects of NFET-only and PFET-only designs 500, 504, such as number of inverters 508, 512 and feature sizes, for example channel length and width, are designed to be the same. In other words, the only difference between NFET-only and PFET-only designs 500, 508 is that their dopings are complementary in charge type.

FIG. 6 illustrates an exemplary IC chip 600 that incorporates instantiations 604, 608 of NFET-only and PFET-only oscillator designs 500, 504 of FIG. 5. In this example, the layout of the NFETs and PFETs (not shown individually) is done in accordance with contemporary practice, i.e., with the NFETs and PFETs formed in corresponding respective NFET regions 612A-B and PFET regions 616A-B. As will be understood by those skilled in the art, each of NFET and PFET regions 612A-B, 616A-B are functionally partitioned into corresponding respective N-type inverter regions 620 and P-type inverter regions 624 by providing suitable wiring in the wiring layers (not shown) of IC chip 600. With this arrangement, PFET-only ring oscillator 608 is conveniently nested within NFET-only ring oscillator 604. An advantage to this configuration is that since it uses conventional CMOS cell library circuit layout techniques, all electrical effects, such as shallow trench isolation, N-well scattering, etc., are consistent across NFET-only and PFET-only ring oscillators 604, 608 and other circuitry 628 aboard IC chip 600. IC chip 600 also includes test points 632 that allow the frequencies of NFET-only and PFET-only ring oscillators 604, 608 to be tested after IC chip 600 has been fabricated. As mentioned above, it is these measured values that are used in screening method 400. The layout of NFET-only and PFET-only ring oscillators 604, 608 and test points 632 may be standardized into a standard cell library circuit so that it may be readily incorporated into differing CMOS-based chip designs.

Before returning to the description of exemplary screening method 400 of FIG. 4, examples of simple homogeneous inverters 700, 704 suitable for use as, respectively, homogeneous inverters 504, 508 are provided in FIGS. 7A-B. FIG. 7A illustrates an NFET-only bootstrap inverter 700 that comprises an input 708, an output 712, and four NFETs 716A-D connected as shown in FIG. 7A. When input 708 is high, NFET 716A is on and holds output 712 low. NFET 716D charges up capacitor NFET 716C to VDD minus threshold. When input 708 goes low, NFET 716A turns off, allowing NFET 716B to pull up output 712, which pulls bootstrap capacitor NFET 716C above VDD, which overdrives the threshold of NFET 716B so that the output reaches VDD.

FIG. 7B illustrates a PFET-only bootstrap inverter 704 that is complementary to NFET-only bootstrap inverter 700 of FIG. 7B. In FIG. 7B, PFET-only bootstrap inverter 704 comprises an input 720, an output 724, and four PFETs 728A-D connected as shown. When input 720 is low, PFET 728A is on and holds output 724 high. NFET 728D charges up capacitor NFET 728C to ground plus threshold. When input 720 goes high, NFET 728A turns off, allowing NFET 728B to pull down output 724, which pulls bootstrap capacitor NFET 728C below ground, which overdrives the threshold of NFET 728B so that the output reaches the ground voltage. It is noted that while homogeneous bootstrap inverters 700, 704 have been shown, there may be other transistor-homogeneous inverters that may be used in accordance with the present invention.

Referring back to FIG. 4, once the NFET-only and PFET-only oscillator designs have been obtained, at step 410 the oscillator designs are simulated, or modeled, using suitable simulation software, such as SPICE (Simulation Program with Integrated Circuit Emphasis) or any SPICE-like variant. At step 415, the NFET-only and PFET-only ring oscillator models are subjected to computational simulation analysis, such as the Monte Carlo method, that uses differing values of process parameters to calculate values of a set of four parameters relating to the NFET-only and PFET-only ring oscillators that result from the varying process parameters. The process parameters used in this analysis are those parameters that are known to vary and cause chip-to-chip, wafer-to-wafer, and lot-to-lot variations that affect as-fabricated IC performance. The four parameters calculated during the simulation analysis are: 1) the NFET-only ring oscillator period, PER_N; 2) the PFET-only oscillator period PER_P; 3) the ratio of NFET-only ring oscillator period to PFET-only, RATIO_N2P; and 4) the ratio of PFET-only ring oscillator period to NFET-only, RATIO_P2N. At step 420, the mean and standard deviation of each of these four parameters are calculated. As an example, Table I illustrates statistics, here mean and ±3 σ, calculated for NFET-only and PFET-only ring oscillators designed for a 65 NM CMOS process.

	TABLE I
		−3σ	Mean	+3σ
	Parameter	(ns)	(ns)	(ns)
	PER_N	326.6	591.9	946.4
	PER_P	695.2	1216.8	1862.1
	RATIO_N2P	0.2852	0.4915	0.7563
	RATIO_P2N	1.3222	2.0346	3.5063

With these statistics calculated, screening method 400 can proceed to step 425 at which a set of test screening limit boundaries can be determined and set.

The determining and setting of such test screening limit boundaries can be illustrated in the context of the example of Table I, above, and the scattergram 800 shown in FIG. 8. Scattergram 800 shows data points 804 of the PFET-only ring oscillator periods versus NFET-only ring oscillator periods for the simulated 65NM CMOS NFET-only and PFET-only ring oscillators as determined from the simulation analysis. As will be understood by those skilled in the art, each data point 804 corresponds to a corresponding set of values for the variable process parameters at issue, as selected by the chosen simulation method, for example, the Monte Carlo method, during the simulation analysis. Assuming for the sake of this example that ±3 σ of the periods PER_N, PER_P of the NFET-only and PFET-only ring oscillators are satisfactory gross boundaries for acceptable performance envelope 808, lower and upper boundaries 812A-B for the NFET period PER_N are set to the corresponding respective values of 326.6 ns and 946.4 ns, and lower and upper boundaries 816A-B for the PFET period PER_P are set to the corresponding respective values of 695.2 ns and 1862.4 ns.

In addition to the 3 σ lower and upper boundaries 812A-B, 816A-B on the NFET and PFET periods PER_N, PER_P, the boundaries of acceptable performance envelope 808 also include lower and upper ratio test screening limit boundaries 820, 824 that are used during screening (see below) to screen-out as-fabricated ICs having measured NFET-to-PFET device performance mismatch points that fall in the potential SPQL exposure regions 828, 832 that generally correspond, respectively, to potential SPQL exposure regions 302, 304 of FIG. 3. Lower and upper ratio test screening boundaries 820, 824 are determined as follows.

At the nominal values, the ratio of NFET-only ring oscillator period to PFET-only ring oscillator period, RATIO_N2P, is simply equal to the ratio of the nominal value of the NFET-only ring oscillator period PER_N to the nominal value of the PFET-only ring oscillator period PER_P, and the ratio of NFET-only ring oscillator period to PFET-only, RATIO_P2N is simply the inverse of that ratio. But, at the ±3 σ end points, the 3 σ frequency offset of one oscillator to the absolute 3 σ frequency limit of the other oscillator needs to be determined. For the NFET-to-PFET ratios, the following equation can be written:

PER_—N/(PER_—P×Multiplier)=RATIO_—N2P   {1}

where PER_N is the value of the NFET period at a given statistic (e.g., ±3 σ), PER-P is the value of PFET period at the given statistic, RATIO-N2P is the value of the NFET-to-PFET ratio at the given statistic and Multiplier is a PFET multiplier value that satisfies Equation {1}. Rearranging Equation {1} allows for solution of Multiplier:

Multiplier=PER_—N/(PER_—P×RATIO_—N2P)   {2}

Similarly for the PFET-to-NFET ratios, Equation {2} becomes:

Multiplier=PER_—P/(PER_—N×RATIO_—P2N)   {3}

Appropriate Multipliers can then be used to calculate the endpoints 820A-B, 824A-B of lower and upper ratio test screening boundaries 820, 824, respectively, as they fall along the corresponding respective 3 σ lower and upper boundaries 812A-B, 816A-B.

For the ±3 σ example of Table I and FIG. 8, endpoints 820A-B of lower ratio test screening boundary 820 along −3 σ lower boundary 816A of the PFET period and +3 σ upper boundary 812B of the NFET period are calculated as follows. First, from Table I, above, the −3 σ values of PER_P, PER_N and RATIO_P2N are, respectively, 695.2 ns, 326.6 ns and 1.3222. Inserting these values into Equation {3} shows that Multiplier=695.2/(326.6×1.3222)=1.610. Multiplying the −3 σ value of PER_N, i.e., 326.6 ns, by 1.610 yields a calculated PER_N of 525.8 ns. Consequently, the coordinates of endpoint 820A on scattergram 800 is (525.8, 695.2).

Similarly, endpoint 620B along +3 σ upper boundary 812B is calculated. First, from Table I, above, the +3 σ values of PER_N, PER_P and RATIO_N2P are, respectively, 946.4 ns, 1862.1 ns and 0.7563. Inserting these values into Equation {2} shows that Multiplier=946.4/(1862.1×0.7563)=0.672. Multiplying the +3 σ value of PER_P, i.e., 1862.1 ns, by 0.672 yields a calculated PER_N of 1214.1 ns. Consequently, the coordinates of endpoint 820B on scattergram 800 is (946.4, 1214.1).

Endpoints 824A-B of upper ratio test screening boundary 824 along +3 σ upper boundary 816B of the PFET period and −3 σ lower boundary 812A of the NFET period are similarly calculated as follows. First, from Table I, above, the +3 σ values of PER_P, PER_N and RATIO_P2N are, respectively, 1862.1 ns, 946.4 ns and 3.5063. Inserting these values into Equation {3} shows that Multiplier=1862.1/(946.4×3.5063)=0.5611. Multiplying the +3 σ value of PER_N, i.e., 946.4 ns, by 0.5611 yields a calculated PER_N of 531.1 ns. Consequently, the coordinates of endpoint 824A on scattergram 800 is (531.1, 1862.1).

Similarly, endpoint 824B along −3 σ lower boundary 812A is calculated. First, from Table I, above, the +3 σ values of PER_N, PER_P and RATIO_N2P are, respectively, 326.6 ns, 695.2 ns and 0.2852. Inserting these values into Equation {2} shows that Multiplier=326.6/(695.2×0.2852)=1.648. Multiplying the −3 σ value of PER_P, i.e., 695.2 ns, by 1.648 yields a calculated PER_N of 1145.5 ns. Consequently, the coordinates of endpoint 824B on scattergram 800 is (326.6, 1145.5).

With the endpoints 820A-B, 824A-B of lower and upper ratio test screening boundaries 820, 824 known, it is a simple matter to calculate the coordinates of any point along either of these boundaries, since they are simply straight lines. It is noted that while the foregoing example is based on ±3 σ performance limits, the foregoing mathematics can be applied to any multiples of the standard deviation desired.

After an acceptable performance envelope, such as performance envelope 808, has been defined, it can be used to screen chips or dies manufactured to contain instantiations of the NFET-only and PFET-only ring oscillator designs, such as ring oscillator designs 500, 504 of FIG. 5, used to obtain the subject performance envelope. Consequently, at step 430 a chip or die is tested to determine the frequencies (periods) of the NFET-only and PFET-only oscillators onboard the chip or die. Then, at step 435 these measured frequencies are compared to the subject performance envelope. If the measured frequencies (periods) fall within the performance envelope, at step 440 the chip or die may be marked as passing the NFET-to-PFET device performance offset screening. However, if the measured frequencies (periods) fall outside the performance envelope, at step 445 the chip or die may be marked as failing the NFET-to-PFET device performance offset screening. Steps 430, 435, 440 and 445 may be repeated for as many chips or dies that remain to be tested.

FIG. 9 shows a block diagram of an example design flow 900. Design flow 900 may vary depending on the type of IC being designed. For example, a design flow 900 for building an application specific IC (ASIC) may differ from a design flow 900 for designing a standard component. Design structure 920 is preferably an input to a design process 910 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure 920 comprises an integrated circuit, e.g. ring oscillator layout 500, 504 in the form of schematics or HDL, a hardware-description language (e.g., Verilog, VHDL, C, etc.). Design structure 920 may be contained on one or more machine readable medium. For example, design structure 920 may be a text file or a graphical representation of an integrated circuit, e.g. ring oscillator 500, 504. Design process 910 preferably synthesizes (or translates) an integrated circuit, e.g. ring oscillator 500, 504 into a netlist 980, where netlist 980 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc. that describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium. This may be an iterative process in which netlist 980 is resynthesized one or more times depending on design specifications and parameters for the circuit.

Design process 910 may include using a variety of inputs; for example, inputs from library elements 930 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 940, characterization data 950, verification data 960, design rules 970, and test data files 985 (which may include test patterns and other testing information). Design process 910 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 910 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.

Design process 910 preferably translates an embodiment of the invention as shown in FIGS. 5, 6, 7A and 7B, along with any additional integrated circuit design or data (if applicable), into a second design structure 990. Design structure 990 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g. information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Design structure 990 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in FIGS. 5, 6, 7A and 7B. Design structure 990 may then proceed to a stage 995 where, for example, design structure 990: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.

Exemplary embodiments have been disclosed above and illustrated in the accompanying drawings. It will be understood by those skilled in the art that various changes, omissions and additions may be made to that which is specifically disclosed herein without departing from the spirit and scope of the present invention.

Claims

1. A design structure embodied in a machine readable medium, the design structure comprising: a CMOS layout that includes: a plurality of PFETs;a plurality of NFETs;a first ring oscillator in which all transistors therein are ones of said plurality of PFETs, said first ring oscillator having a first frequency; anda second ring oscillator in which all transistors therein are ones of said plurality of NFETs, said second ring oscillator having a second frequency; anda plurality of test points in communication with said first and second ring oscillators so as to permit measurement of the first and second frequencies.

2. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

3. The design structure of claim 1, wherein the design structure comprises a netlist.

4. The design structure of claim 1, wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.