The present disclosure relates to integrated circuits (IC), and more specifically, to a structure with a counter doping region between N and P wells under a gate structure to, for example, improve drain-source breakdown voltage.
Laterally diffused metal-oxide semiconductor (LDMOS) field effect transistors (FETs) are used in a variety of integrated circuit applications such as microwave or radio frequency (RF) power amplifiers. An LDMOS FET is an asymmetric power FET designed for low resistance and high drain-source breakdown voltage. These devices use a diffused p-type channel region in a low-doped n-type drain region. Continuing manufacture and operability of LDMOS FETs at advanced technology nodes, e.g., 14 nanometers and beyond, present numerous challenges. One challenge is providing a sufficient drain-source breakdown voltage (BVdss) to ensure operability of the devices. Drain-source breakdown voltage is the drain-to-source voltage at which no more than a particular drain current will flow at a particular temperature with no gate-source voltage. The drain-source breakdown voltage is generally aligned with the actual device breakdown voltage. Typically, drain-source breakdown voltage increases with channel length (i.e., the distance between the drain and source) up to a certain maximum length, e.g., 300 nm at the 14 nm technology node. Most approaches to increase drain-source breakdown voltage in LDMOS FETs thus attempt to lengthen the distance current must travel between the drain and source.
A first aspect of the disclosure is directed to a structure comprising: a gate structure between a first doping region and a second doping region over a substrate; a trench isolation partially under the gate structure and between the gate structure and the second doping region; a first well under and adjacent the first doping region; a second well under and adjacent the second doping region; and a counter doping region abutting and between the first well and the second well, the counter doping region directly underneath the gate structure.
A second aspect of the disclosure includes a method, comprising: forming a trench isolation in a semiconductor substrate; forming a first mask over the semiconductor substrate, the first mask exposing a first region to a first side of and distanced from the trench isolation; using the first mask, forming a first well in the semiconductor substrate in the first region, the first well distanced from the trench isolation; removing the first mask; forming a second mask over the semiconductor substrate, the second mask exposing a second region including a portion of a width of the first well; using the second mask, form a second well in the semiconductor substrate in the second region and a counter doping region in the portion of the width of the first well, the first well and the second well having different dopant types; removing the second mask; forming a first doping region in the first well and a second doping region in the second well on an opposite side of the trench isolation from the first well; and forming a gate structure between the first doping region and the second doping region over the semiconductor substrate.
A third aspect of the disclosure related to a laterally diffused metal-oxide semiconductor (LDMOS) field effect transistor (FET), comprising: a gate structure between a source region and a drain region over a p-type semiconductor substrate; a trench isolation partially under the gate structure and between the gate structure and the drain region; a p-well under and adjacent the source region; an n-well under and adjacent the drain region; and a counter doping region abutting and between the p-well and the n-well, the counter doping region directly underneath the gate structure.
The foregoing and other features of the disclosure will be apparent from the following more particular description of embodiments of the disclosure.
The embodiments of this disclosure will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.
Embodiments of the disclosure provide a structure that provides increased drain-source breakdown voltage for transistor devices at advanced technology nodes, e.g., 14 nanometers and beyond. The structure is advantageous for use with, for example, LDMOS FETs such as used for microwave or RF power amplifiers. The structure may include a gate structure between a first doping region, e.g., a source region, and a second doping region, e.g., a drain region, over a substrate. A trench isolation is partially under the gate structure and between the gate structure and the second doping region (source). A first well is under and adjacent the first doping region (source); and a second well is under and adjacent the second doping region (drain). The structure, in contrast to conventional LDMOS FETs, also includes a counter doping region abutting and between the first well and the second well, the counter doping region being directly underneath the gate structure. The counter doping region includes both n-type and p-type dopants, and provides a mechanism to increase drain-source breakdown voltage in a non-complex manner and without increasing the footprint of the device.
Embodiments of the disclosure will be described relative to a structure 100 (
Doping is a process of introducing impurities (dopants) into the semiconductor substrate, or elements formed on the semiconductor substrate, and is often performed with a mask (or previously-formed, elements in place) so that only certain areas of the substrate will be doped. For example, as will be described, doping is used to form a source region and a drain region of a field effect transistor (FET). An ion implanter is typically employed for the actual implantation. An inert carrier gas such as nitrogen is usually used to bring in the impurity source (dopant). However, in-situ formation of dopant containing semiconductor may also be employed, e.g., deposition and/or epitaxy. Dopants may be n-type or p-type. N-type is an element introduced to a semiconductor to generate free electrons (by “donating” electrons to the semiconductor), and must have one more valance electron than the semiconductor. N-type dopants in silicon (Si) may include but are not limited to: phosphorous (P), arsenic (As), antimony (Sb). P-type is an element introduced to a semiconductor to generate free holes (by “accepting” electrons from the semiconductor atom and “releasing” holes at the same time), and acceptor atom must have one valence electron less than the host semiconductor. P-type dopants may include but are not limited to: boron (B), indium (In) and gallium (Ga).
Trench isolation 120 may be formed in semiconductor substrate 110 in any now known or later developed manner. Generally, a trench 122 is etched into semiconductor substrate 110 and filled with an insulating material. Typically, trench isolations, sometimes referred to as shallow trench isolations (STI), are used to isolate one region of the substrate from an adjacent region of the substrate. In accordance with embodiments of the disclosure, however, trench isolation 120 is within a final device to elongate a channel length of the device. Each trench isolation 120 may be formed of any currently-known or later developed substance for providing electrical insulation, and as examples may include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) that include atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen (H), thermosetting polyarylene ethers, a spin-on silicon-carbon containing polymer material, near frictionless carbon (NFC), or layers thereof. In one embodiment, trench isolation 120 includes silicon oxide.
The upper part of
As shown in the cross-section in the lower part of
Second well 160 may extend beside each side and under trench isolation 120. Second well 160 may extend to any depth appropriate for the type of device being formed, and may have any appropriate second dopant concentration. Counter doping region 162 will extend to the depth of the least deep well 140, 160. As illustrated, counter doping region 162 is spaced from trench isolation 120, i.e., by drain extension length Ld as defined by first mask 130. In one non-limiting example, at a 14 nanometer technology node, Ld may be between 0.2 and 0.4 micrometers.
Referring to the cross-sectional view of
Counter doping region 162 includes both n-type dopants and p-type dopants. As noted, in one embodiment, semiconductor substrate 110 may include a p-type dopant, the first dopant in first well 140 may include an n-type dopant, and the second dopant in second well 160 may include a p-type dopant. A first dopant concentration may be in first p-well 140, a second dopant concentration may be in second n-well 160, and counter doping region 162 may include the first dopant concentration and the second dopant concentration.
With counter doping region 162 including both n-type dopants and p-type dopants, it creates a more gradient junction than current structures. Consequently, structure 100 and LDMOS FET 102 can sustain higher drain-source breakdown voltages (BVdss), compared to conventional devices. As shown in
In the example shown in the table, drain-source breakdown voltage (BVdss) can be increased anywhere from 8.6V to 9.5V, depending on width W2 of counter doping region 162. Counter doping region 162 also can improve saturation current (Idsat) without leakage degradation. In one non-limiting example, saturation current (Idsat) was increased from 669 to 757 micro-Amperes per micrometer, depending on the width W2 of counter doping region 162. Additional increases may be possible with widening of counter doping region 162 from 100 nanometers to 200 nanometers. It is noted that while counter doping region 162 provides the above advantages, it does not increase device footprint.
The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about”, “approximately” and “substantially”, are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s).
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.