Embodiments of the present invention relate to an alignment technical field, and particularly relate to a substrate alignment mark and a fabricating method thereof, and a substrate.
Up to now, liquid crystal display technology has become well-established, and the major competition among various panel companies increasingly focuses on increase in yield rate and reduction in costs. Photolithography is a necessary process in manufacturing a thin film transistor liquid crystal display (“TFT-LCD”); when an exposure machine performs an exposure process, in order to achieve satisfactory alignment between patterns in respective layers, alignment marks are usually fabricated in a peripheral region of a substrate to ensure alignment precision.
Alignment marks of the conventional technology are usually fabricated in a same layer as a gate electrode or a source/drain electrode of a thin film transistor (“TFT”); during a production process, in a plating, depositing, or sputtering process or the like for forming a gate electrode metal layer thin film or a source/drain electrode metal layer thin film, uneven metal film formation may occur, making the alignment marks under a microscope appear to be small black dots in alignment and unable to be identified effectively, and then alignment is not achieved, thus leading to increase in defective rate.
In order to solve the above-mentioned technical problem, an embodiment of the present invention provides a substrate alignment mark; the substrate alignment mark comprises a first alignment mark pattern and a second alignment mark pattern that are formed in a different-layer structure on a substrate; the first alignment mark pattern and the second alignment mark pattern are provided with centers thereof aligned and without overlapping portions therebetween.
As for the above-mentioned substrate alignment mark, in an example, the second alignment mark pattern is located in a region enclosed by the first alignment mark pattern; both the first alignment mark pattern and the second alignment mark pattern are of hollow structures, or the first alignment mark pattern is of a hollow structure and the second alignment mark pattern is of a solid structure.
As for the above-mentioned substrate alignment mark, in an example, the first alignment mark pattern and the second alignment mark pattern are of similar structures.
As for the above-mentioned substrate alignment mark, in an example, both the first alignment mark pattern and the second alignment mark pattern are of hollow cross-type structures, or the first alignment mark pattern is of a hollow cross-type structure and the second alignment mark pattern is of a solid cross-type structure.
As for the above-mentioned substrate alignment mark, in an example, the first alignment mark pattern and the second alignment mark pattern are of different structures.
As for the above-mentioned substrate alignment mark, in an example, the first alignment mark pattern is of a hollow cross-type structure and the second alignment mark pattern is of a ring structure, or the first alignment mark pattern is of a hollow cross-type structure and the second alignment mark pattern is of a solid circle structure.
In addition, an embodiment of the present invention further provides a substrate, the substrate is provided with an alignment mark thereon, and the alignment mark comprises any of the above-mentioned substrate alignment marks.
As for the above-mentioned substrate, in an example, a thin film transistor is formed on the substrate; the first alignment mark pattern is made from a same metal layer as a gate electrode of the thin film transistor; the second alignment mark pattern is made from a same metal layer as a source/drain electrode of the thin film transistor.
Accordingly, an embodiment of the present invention further provides a fabricating method of a substrate alignment mark, comprising a step of forming a first alignment mark pattern and a step of forming a second alignment mark pattern; the first alignment mark pattern and the second alignment mark pattern are formed in a different-layer structure on a substrate, and provided with centers thereof aligned and without overlapping portions therebetween.
As for the above-mentioned fabricating method of a substrate alignment mark, in an example, the fabricating method further comprises a step of forming a thin film transistor, the step of forming the first alignment mark pattern comprises forming the first alignment mark pattern in a same layer as a gate electrode of the thin film transistor; the step of forming the second alignment mark pattern comprises forming the second alignment mark pattern in a same layer as a source/drain electrode of the thin film transistor.
With reference to accompanying drawings and embodiments, specific implementation of the present invention will be described in detail in the following. The following embodiments are used to describe the present invention and not limitative to the scope of the present invention.
It is to be noticed that the following terms “first,” “second,” “third,” are only used to describe the present invention, and does not indicate relative importance.
In order to increase identification success rate of alignment marks during a substrate manufacturing process, this embodiment provides a fabricating method of a substrate alignment mark, the method comprising a step of forming a first alignment mark pattern and a step of forming a second alignment mark pattern. The first alignment mark pattern and the second alignment mark pattern are formed in a different-layer structure on a substrate (here the different-layer structure refers to patterns formed by thin films in different layers on the substrate, and correspondingly, a same-layer structure refers to patterns formed by a thin film in the same layer on the substrate), and are provided with centers thereof aligned with each other, namely, the centers of the first alignment mark pattern and the second alignment mark pattern coincide with each other from top to bottom, and located in a line, so that when alignment is performed with the two alignment marks respectively, alignment uniformity can be maintained. The first alignment mark pattern and the second alignment mark pattern are provided without overlapping portions, to guarantee that, when one of the alignment marks cannot be identified, alignment process is not affected by identifying the other alignment mark.
By fabricating two alignment marks with thin films in different layers on a substrate, the chance that the two layers forming the alignment marks are suffered from uneven film formation simultaneously is very low, so when uneven film formation occurs in the process of forming one of the alignment marks, causing the alignment mark to be unidentifiable in alignment, the alignment can be performed by identifying the other alignment mark, thus increasing identification success rate of the alignment marks.
According to the above embodiment, it is very easy for a person skilled in the art to perceive that more pairs of alignment mark patterns can be fabricated and provided with centers thereof aligned, and any two of the alignment mark patterns are formed in a different-layer structure on the substrate, and the work principle thereof is the same as that of the case where two alignment mark patterns are provided, leading to higher an identification success rate of alignment marks; but the increase in the success rate is limited while fabricating costs will be added, so in general, it is still satisfactory to fabricate two alignment mark patterns only.
With reference to an example of a manufacturing process of an array substrate comprising a bottom-gate-structure TFT, the fabricating process of the substrate alignment mark in this embodiment of the present invention will be described in the following.
Firstly, a first alignment mark pattern is formed in a same layer as a gate electrode of a transistor thin film. For example, after forming a gate electrode metal layer thin film on a base substrate (for example, a glass substrate, quartz substrate or transparent resin substrate, as illustrated by reference sign 3 in
Then, a second alignment mark pattern is formed in a same layer as a source/drain electrode of the thin film transistor. For example, a gate insulating layer, an active layer (the two layers are illustrated by reference sign 4 in
It is to be noted that, the fabricating method of substrate alignment mark provided by the embodiment of the present invention hereby is only an illustrative example, and suitable for all substrates that need to fabricate an alignment mark, but not limited to an array substrate comprising a bottom-gate-structure TFT. Further, the technical solution that the second alignment mark pattern is formed with a half-tone or gray-tone mask to perform an exposing and developing process is described above, however, as an alternative, it is also suitable to use a common full-tone mask to perform an exposing and developing process so as to form the second alignment mark pattern.
Accordingly, this embodiment provides a substrate alignment mark. As illustrated in
In order to achieve that the first alignment mark pattern 1 and the second alignment mark pattern 2 are provided without overlapping portions, in this embodiment, the second alignment mark pattern 2 can be designed to be located within a region which is enclosed by the first alignment mark pattern, and the first alignment mark pattern 1 is of a hollow structure, then the second alignment mark pattern 2 can be either of a hollow structure or a solid structure.
Further, the first alignment mark pattern 1 and the second alignment mark pattern 2 can be of similar structures, namely the first alignment mark pattern 1 and the second alignment mark pattern 2 are the same in profile but different in size only, for example, the first alignment mark pattern 1 is of a hollow cross-type structure and the second alignment mark pattern 2 can be either of a hollow cross-type structure, as illustrated in
This embodiment provides a substrate with an alignment mark thereon, and the alignment mark uses the substrate alignment mark in the second embodiment. Because of an increase in identification success rate of alignment marks, defective rate caused by failure to identify alignment marks in manufacturing process of a substrate is noticeably decreased.
With regard to a TFT-LCD array substrate, a thin film transistor is formed on the array substrate; in practice, as illustrated in
It is can been seen from the above embodiments that, in the substrate alignment mark and the fabricating method thereof provided by the embodiments of the present invention, two alignment mark patterns are formed in a different-layer structure on a substrate, when uneven film formation occurs in the process of forming one of the alignment marks, causing the alignment mark to be unidentifiable in alignment, the alignment can be performed by identifying the other alignment mark, thus identification success rate of alignment marks is increased, and then defective rate caused by failure to identify alignment marks in manufacturing process of the substrate is noticeably decreased.
The embodiments of the present invention provide a substrate alignment mark and a fabricating method thereof, so as to resolve the problem that alignment marks are unidentifiable in alignment due to uneven film formation in the process of fabricating the alignment marks; the embodiments of the present invention further provide a substrate with the above-mentioned substrate alignment mark formed thereon, decreasing the defective rate caused by failure to identify alignment marks in manufacturing process of the substrate.
The above are only part of embodiments of the present invention; it is should be pointed out that, for a common person skilled in the art, modifications and equivalents can further be made without departing from the technical principle of the present invention, and these modifications and equivalents should be within the scope of the present invention.
Number | Date | Country | Kind |
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201310075174.X | Mar 2013 | CN | national |
Filing Document | Filing Date | Country | Kind |
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PCT/CN13/78091 | 6/27/2013 | WO | 00 |