BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a plan view showing the outline of a configuration of a substrate processing system;
FIG. 2 is a front view of the substrate processing system 1 in FIG. 1;
FIG. 3 is a rear view of the substrate processing system 1 in FIG. 1;
FIG. 4 is an explanatory view of a longitudinal section showing the outline of the configuration of a planarization unit;
FIG. 5 is an explanatory view of a transverse section showing the outline of the configuration of the planarization unit;
FIG. 6 is an explanatory view showing the appearance on a wafer during planarization processing;
FIG. 7 is a flowchart of the wafer processing;
FIG. 8 is an explanatory view of a longitudinal section of the wafer showing the state in which a coating insulating film is formed on a base pattern;
FIG. 9A is an explanatory view of a longitudinal section showing the state in which a brush is pressed against the center of the wafer, FIG. 9B is an explanatory view of a longitudinal section showing the state in which the brush is horizontally moved, and FIG. 9C is an explanatory view of a longitudinal section showing the state in which the brush reaches a position outside the wafer;
FIG. 10 is a flowchart of the wafer processing including a low-temperature heating step;
FIG. 11 is a flowchart of the wafer processing including an ultraviolet irradiation step;
FIG. 12 is a rear view of the substrate processing system including a UV irradiation unit;
FIG. 13 is a flowchart of the wafer processing including a high-temperature heating step;
FIG. 14 is an explanatory view of a longitudinal section of the wafer showing the state of projections and depressions on the front surface of the coating insulating film;
FIG. 15A is an explanatory view of a longitudinal section of the wafer showing the state in which planarization is performed with a thin coating insulating film being left, FIG. 15B is an explanatory view of a longitudinal section of the wafer showing the state in which the coating insulating film is hardened, and FIG. 15C is an explanatory view of a longitudinal section of the wafer showing the state in which the thin coating insulating film is etched;
FIG. 16 is a flowchart of the wafer processing including a coating film forming step;
FIG. 17 is an explanatory view of a longitudinal section of the wafer showing the state in which the thin coating insulating film is formed;
FIG. 18 is an explanatory view of a longitudinal section showing a multilayer wiring structure in which an element isolation trench is formed in the base pattern;
FIG. 19 is an explanatory view of a longitudinal section showing the multilayer wiring structure in which a transistor is formed on the base pattern;
FIG. 20 is an explanatory view of a longitudinal section showing the multilayer wiring structure in which aluminum wirings are formed on the base pattern;
FIG. 21 is a plan view of the wafer for explaining control of solvent supply in the planarization step;
FIG. 22 is a side view showing the state in which the brush is moved to the end portion of the wafer;
FIG. 23 is a side view showing the state in which the brush is separated from the wafer after the brush is reciprocated between the center and the end portion of the wafer;
FIG. 24 is a side view showing the state of solvent discharge by a combined nozzle;
FIG. 25 is a side view showing the state of blow of a nitrogen gas by the combined nozzle;
FIG. 26 is a side view showing the appearance in which a solution film at the center of the wafer is removed by the nitrogen gas;
FIG. 27 is a side sectional view showing the appearance in which the brush is cleaned in a cleaning bath provided at a waiting portion; and
FIG. 28 is a sectional view of the brush having a solvent supply path at its center.