I. Field of the Disclosure
The technology of the disclosure relates generally to bulk and silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) devices, and particularly to isolation of transistors formed in such devices.
II. Background
Silicon wafers are commonly used for providing semiconductor devices. For example, in a bulk complementary metal oxide semiconductor (CMOS) device, transistors are formed in a bulk silicon body layer. Shallow trench isolation (STI) is employed to provide some isolation between adjacent transistors in the CMOS device. However, the bulk silicon body layer of the transistors in the CMOS device is connected. As a result, the transistors in the CMOS device are not completely isolated. Also, bulk CMOS devices are not particularly suited for radio frequency (RF) applications in which higher voltages are coupled (e.g., 25V), as bulk CMOS devices encounter device breakdown at higher voltage levels.
To provide isolation between adjacent transistors in a semiconductor device, silicon-on-insulator (SOI) wafers have been introduced. In SOI wafers, transistors are formed in thin layers of silicon that are isolated from a main body of an SOI wafer handle substrate by a layer of an electrical insulator, usually silicon dioxide. The silicon layer thickness ranges from several microns for electrical power switching devices to less than 500 Angstroms for high-performance microprocessors. Isolating an active transistor from the rest of a silicon substrate reduces electrical current leakage that would otherwise degrade the performance of the transistor. Since the area of electrically active silicon is limited to the immediate region around the transistor, switching speeds are increased and sensitivity to “soft errors” is greatly reduced.
In this regard,
During the bonding process of the SOI wafer 100 in
Aspects disclosed in the detailed description include substrate-transferred, deep trench isolation silicon-on-insulator (SOI) semiconductor devices formed from bulk semiconductor wafers. Related methods and circuits are also disclosed. In this regard, in one aspect, a bulk semiconductor wafer is provided. The bulk semiconductor wafer may be a complementary metal oxide semiconductor (CMOS) device. The bulk semiconductor wafer includes a bulk body layer, also known as a “bulk body.” The bulk body may be a silicon bulk body. One or more transistors are formed in the bulk body of the bulk semiconductor wafer. Deep trenches are formed between the transistors formed in the bulk body (e.g., in a front end-of-line (FEOL) process) to provide current leakage isolation between the transistors. However, to prevent the bulk body in the bulk semiconductor wafer from electrically interconnecting the transistors, and defeating the isolation of the deep trenches, aspects disclosed herein involve the bulk body being thinned near, at, or beyond the back side of the deep trenches formed in the bulk body. As a result, the bulk body of the transistors is separated into separate bulk bodies for each transistor isolated by the deep trenches. An insulation substrate, such as glass for example, is then bonded to the bulk semiconductor wafer (e.g., in a back end-of-line (BEOL) process) to form an SOI wafer. In this manner, the residual bulk bodies of the transistors are isolated between the deep trenches and the insulation substrate to reduce or avoid leakage current between transistors. However, by the SOI wafer being formed from a bulk semiconductor wafer, the formation of a semiconductor layer between the insulation substrate and the transistors during fabrication is reduced or avoided, thereby reducing non-linearity and power loss of the transistors. This may allow the SOI wafer to be particularly suited for semiconductor devices for radio-frequency (RF) applications, as a non-limiting example.
In this regard, in one exemplary aspect, an SOI wafer is provided. The SOI wafer comprises an insulation substrate comprising a top side and a back side. The SOI wafer also comprises an active semiconductor layer disposed above the insulation substrate, the active semiconductor layer comprising a bulk body and a plurality of transistors formed in the bulk body. The SOI wafer also comprises one or more deep trenches disposed in the bulk body to the top side of the insulation substrate and between adjacent transistors among the plurality of transistors.
In another exemplary aspect, an SOI wafer is provided. The SOI wafer comprises a means for insulating comprising a top side and a back side. The SOI wafer also comprises a means for providing an active semiconductor layer disposed above the means for insulating, the means for providing the active semiconductor layer comprising a bulk body and a plurality of transistors formed in the bulk body. The SOI wafer also comprises a means disposed in the bulk body to the top side of the means for insulating, for providing isolation between adjacent transistors among the plurality of transistors.
In another exemplary aspect, a method of fabricating an SOI wafer is provided. The method comprises providing a bulk body layer comprising a top side and a back side. The method also comprises forming an active semiconductor layer comprising one or more transistors in the top side of the bulk body layer. The method also comprises forming one or more deep trenches in the top side of the bulk body layer between adjacent transistors among the one or more transistors. The one or more deep trenches each comprises a top side disposed toward the top side of the bulk body layer and a back side disposed toward the back side of the bulk body layer. The method also comprises removing a portion of the bulk body layer from the back side of the bulk body layer towards the back side of the one or more deep trenches to form a residual bulk body. The method also comprises disposing an insulation substrate on a back side of the residual bulk body.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include substrate-transferred, deep trench isolation silicon-on-insulator (SOI) semiconductor devices formed from bulk semiconductor wafers. Related methods and circuits are also disclosed. In this regard, in one aspect, a bulk semiconductor wafer is provided. The bulk semiconductor wafer may be a complementary metal oxide semiconductor (CMOS) device. The bulk semiconductor wafer includes a bulk body layer, also known as a “bulk body.” The bulk body may be a silicon bulk body. One or more transistors are formed in the bulk body of the bulk semiconductor wafer. Deep trenches are formed between the transistors formed in the bulk body (e.g., in a front end-of-line (FEOL) process) to provide current leakage isolation between the transistors. However, to prevent the bulk body in the bulk semiconductor wafer from electrically interconnecting the transistors, and defeating the isolation of the deep trenches, aspects disclosed herein involve the bulk body being thinned near, at, or beyond the back side of the deep trenches formed in the bulk body. As a result, the bulk body of the transistors is separated into separate bulk bodies for each transistor isolated by the deep trenches. An insulation substrate, such as glass for example, is then bonded to the bulk semiconductor wafer (e.g., in a back end-of-line (BEOL) process) to form an SOI wafer. In this manner, the residual bulk bodies of the transistors are isolated between the deep trenches and the insulation substrate to reduce or avoid leakage current between transistors. However, by the SOI wafer being formed from a bulk semiconductor wafer, the formation of a semiconductor layer between the insulation substrate and the transistors during fabrication is reduced or avoided, thereby reducing non-linearity and radio-frequency (RF) power loss of the transistors. This may allow the SOI wafer to be particularly suited for semiconductor devices for radio-frequency (RF) applications, as a non-limiting example.
In this regard,
As discussed in more detail below, the finalized SOI wafer 200 in
Also, by the finalized SOI wafer 200 in
In this regard, with reference to
Next, as shown in
As non-limiting examples, a portion of the bulk body layer 302 could be removed so that a back side 310 of the bulk body 214 is near the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2). For example, the back side 310 of the bulk body 214 may be processed to be within one (1) to ten (10) micrometers (μm), such as from three (3) to five (5) μm for example, from the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2). In this case, the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2) are not fully exposed. For example, the deep trenches 218(1), 218(2) can be formed in the bulk semiconductor wafer 300 to be ten (10) to fifteen (15) μm deep.
Also, the removal process used to remove a portion of the bulk body layer 302 may not be able to fully sense the exact location of the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2). Thus, the amount of the bulk body layer 302 removed could be distance based.
Alternatively, enough of a portion of the bulk body layer 302 could be removed to expose the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2). Thus, the back side 310 of the bulk body 214 could be removed at the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2). In this example, the removal process used to remove a portion of the bulk body layer 302 may be able to use the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2) as a stop (e.g., a grind stop) for the removal process. The back side 310 of the bulk body 214 could also be removed beyond the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2).
Now that a portion of the bulk body layer 302 is removed towards the back sides 216(1), 216(2) of the deep trenches 218(1), 218(2), the insulation substrate 212 can be disposed on the bulk semiconductor wafer 300 to form the SOI wafer 200D shown in
Another optional process may be to add another oxidation or coating layer 314 to the insulation substrate 212 to prevent or reduce impurities from being formed in the insulation substrate 212. For example, the coating layer 314 may be a polymer material.
Lastly, in this example, the carrier wafer 304 can be detached from the SOI wafer 200D in
Substrate-transferred, deep trench isolation SOI semiconductor devices formed from bulk semiconductor wafers according to aspects disclosed herein, may be provided in or integrated into in any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a smart phone, a tablet, a phablet, a computer, a portable computer, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, and an automobile.
In this regard,
Other devices can be connected to the system bus 510. As illustrated in
The CPU(s) 504 may also be configured to access the display controller(s) 524 over the system bus 510 to control information sent to one or more displays 528. The display controller(s) 524 sends information to the display(s) 528 to be displayed via one or more video processors 530, which process the information to be displayed into a format suitable for the display(s) 528. The display(s) 528 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer-readable medium and executed by a processor or other processing device, or combinations of both. The master and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flow chart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.