Patent Application
20180040819
The present application relates to integrated circuit fabrication, and more particularly, to the fabrication of mixed ionic electronic conductor-based memory cell access devices using a subtractive etch process.
Mixed ionic electronic conductors (MIEC) are being explored as access devices for non-volatile memories such as, for example, phase-change memory, resistive random access memory, and spin-torque transfer random access memory. MIEC-based access devices having high voltage margins for use in large memory arrays are desirable. Study shows that MIEC voltage margins increase as the confined volume of MIEC material decreases.
The MIEC-based memory cell access devices are typically formed using an additive damascene process in which a dielectric material layer is patterned to include vias therein. The MIEC material is subsequently deposited within the vias and thereafter any MIEC material that is located outside the vias is removed utilizing a planarization process, e.g., chemical mechanical planarization (CMP).
The present application provides methods of forming MIEC-based memory cell access devices using a subtractive etch process.
In one embodiment, the method includes first forming a MIEC material layer on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode. A metal layer is subsequently formed on the MIEC material layer. After forming a metallic hard mask portion on the metal layer, portions of the metal layer and portions of the MIEC material layer that are not covered by the metallic hard mask portion are removed.
In another embodiment, the method includes first forming alternating MIEC material layers and metal layers on a bottom electrode and a dielectric material layer laterally surrounding the bottom electrode. A metallic hard mask portion is subsequently formed on a topmost metal layer in the alternating MIEC material layers and metal layers. Portions of the alternating MIEC material layers and metal layers that are not covered by the metallic hard mask portion are then removed.
The present application will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present application.
Referring to
The substrate 10 may be composed of a semiconductor material. Exemplary semiconductor materials that may be used as substrate 10 include, but are not limited to, Si, SiGe, SiGeC, SiC, Ge alloys GaAs, InAs, InP, carbon-containing materials such as, for example, carbon nanotubes and graphene, and other III/V or II/VI compound semiconductors. In one embodiment, the semiconductor material which can be employed as substrate 10 may be present in a bulk semiconductor substrate. In another embodiment, the semiconductor material which can be employed as substrate 10 may be a topmost layer of a multilayered semiconductor material stack. In yet another embodiment, the semiconductor material that can be employed as substrate 10 can be a topmost layer of a semiconductor-on-insulator substrate.
In some embodiments, the semiconductor material that can be employed as substrate 10 can be single crystalline (i.e., a material in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries). In another embodiment, the semiconductor material that can be employed as substrate 10 can be polycrystalline (i.e., a material that is composed of many crystallites of varying size and orientation; the variation in direction can be random (called random texture) or directed, possibly due to growth and processing conditions). In yet another embodiment of the present application, the semiconductor material that can be employed as substrate 10 can be amorphous (i.e., a non-crystalline material that lacks the long-range order characteristic of a crystal). Typically, the semiconductor material that can be employed as substrate 10 is a single crystalline semiconductor material, such as, for example, single crystalline silicon.
The substrate 10 may be doped, undoped or contain doped and undoped regions therein. For clarity, the doped regions are not specifically shown in substrate 10. Each doped region within the substrate 10 may have the same, or they may have different conductivities and/or doping concentrations.
The substrate 10 can be processed utilizing techniques known in the art to include one or more semiconductor devices such as, for example, transistors, capacitors, diodes, resistors, or other components that are part of integrated circuits. For clarity, the semiconductor devices are not shown in the drawings of the present application.
The first dielectric material layer 20 is formed on the substrate 10. The first dielectric material layer 20 may include a dielectric material such as, for example, silicon dioxide, silicon nitride, or silicon oxyntride. In some embodiments of the present application, the first dielectric material layer 20 may also include a low-k dielectric material having a dielectric constant that is about 4.0 or less. Exemplary low-k dielectric materials include, but are not limited to, organosilicates, silsequioxanes, undoped silicate glass (USG), fluorosilicate glass (FSG), tetraethylorthosilicate (TEOS), SiCOH or borophosphosilicate glass (BPSG). The first dielectric material layer 20 may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or spin coating. The thickness of the first dielectric material layer 20 may be from 100 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.
The first dielectric material layer 20 may include interconnect structures (not shown) to provide electric connections among electric components formed in the substrate 10. The first dielectric material layer 20 may also include memory cells (not shown) embedded therein. For clarity, the interconnect structures and memory cells are not shown in the drawings of the present application.
The second dielectric material layer 30 is formed on the first dielectric material layer 20. The second dielectric material layer 30 may include a dielectric material that is the same as, or different from, the dielectric material of the first dielectric material layer 20. In one embodiment, the second dielectric material layer 30 is composed of a dielectric material that can be selectively etched with respect to the first dielectric material layer 20. For example and when the first dielectric material layer 20 is composed of a dielectric oxide, the second dielectric material layer 30 may be composed of silicon nitride. The second dielectric material layer 30 may be formed by CVD, PECVD or spin coating. The thickness of the second dielectric material layer 30 may be from 10 nm to 1,000 nm, although lesser and greater thicknesses can also be employed.
Following the deposition of the second dielectric material layer 30, the bottom electrode 40 is formed within the second dielectric material layer 30. The bottom electrode 40 is laterally surrounded by the second dielectric material layer 30. In some embodiments of the present application, the bottom electrode 40 can be a top electrode of a memory cell. The bottom electrode 40 may include any suitable conductive material such as, for example, TiN, TaN, W, Al, Cu, Ag, Ir, Pt, Au, Co or Ni. In one embodiment, the bottom electrode 40 can be formed by first patterning the second dielectric material layer 30, utilizing lithography and etching processes known in the art, to provide an opening (not shown) that extends through the second dielectric material layer 30. The lithographic step may include applying a photoresist layer (not shown) to the second dielectric material layer 30, exposing the photoresist layer to a pattern of radiation and developing the pattern into the exposed photoresist layer unitizing a resist developer. The etching step performed to transfer the pattern from the patterned photoresist layer into the second dielectric material layer 30 can include an anisotropic etch which can be a dry etch such as, for example, reactive ion etch (RIE) or a wet etch. After the etch, the patterned photoresist layer can be removed from the structure utilizing a resist stripping process such as, for example, ashing. The opening is then filled with the conductive material by a conventional deposition method such as, for example, CVD, physical vapor deposition (PVD) or plating. The excess conductive material is subsequently removed from the top surface of the second dielectric material layer 30, for example, by CMP. The bottom electrode 40 thus formed has a top surface coplanar with the top surface of the second dielectric material layer 30.
The MIEC material layer 50 is formed on the second dielectric material layer 30 and the bottom electrode 40 as a blanket layer (i.e., as an unpatterned contiguous layer). The MIEC material layer 50 may include a material that is capable of conducting both ions and electronic charge carriers (electrons and/or holes). For example, the MIEC material layer 50 may be composed of a material represented by a formula of MaXbYc, wherein M is a metallic element including but not limited to Cu, Ag, Li, or Zn, X is a Group XIV element including, but not limited to, Ge, Si, Sn or C or a Group VIB transition metal including but not limited to Cr, Mo or W, and Y is a Group XVI or chalcogen element including but not limited to S, Se, Te or O, and wherein a is from 20 to 70 atomic %, b is from 4 to 30 atomic %, and c is from 30 to 60 atomic %. In one embodiment, the MIEC material layer 50 includes Cu8GeS6 or Cu8GeSe6. In some embodiments, combinations of the various elements mentioned above, such as Ag4.7Cu3.3GeS6, could also be used as the MIEC layer 50. The MIEC material layer 50 can be deposited, for example, by PVD, CVD or atomic layer deposition (ALD). The deposition temperature of the MIEC material is typically below 400° C., thus is compatible with low-temperature back-end-of-line (BEOL) semiconductor processing conditions. The thickness of the MIEC material layer 50 that is formed can be from 10 nm to 200 nm, although lesser and greater thicknesses can also be employed.
The metal layer 60 is formed on the MIEC material layer 50 as a blanket layer. The metal layer 60 may include a conductive material that can withstand the etch chemistry employed to etch the overlying metallic hard mask layer 70, thus acting as a barrier to prevent damage to the MIEC material layer 50 during the etching of the metallic hard mask layer 70 subsequently performed. In one embodiment, the metal layer 60 may include Ru, Cu, Ag, Au, Ni, Fe, Pt, Pd, W, Ir or Co. The metal layer 60 may be formed utilizing a conventional deposition method such as, for example, CVD, PECVD or ALD.
The metallic hard mask layer 70 is formed on the metal layer 60 as a blanket layer. The metallic hard mask layer 70 may include a metal nitride, a metal carbide, an elemental metal, an intermetallic alloy, or a combination or a stack thereof. In one embodiment, the metallic hard mask layer 70 includes a metal nitride such as TiN, TaN, WN or an alloy thereof. The metallic hard mask layer 70 may be deposited, for example, by CVD or PVD. The thickness of the metallic hard mask layer 70 can be from 10 to 200 nm, although lesser and greater thickness can also be employed.
The dielectric hard mask layer 80 is formed on the metallic hard mask layer 70 as a blanket layer. The dielectric hard mask layer 80 may include a dielectric oxide or dielectric nitride. In one embodiment, the dielectric hard mask layer 80 is composed of silicon dioxide. The dielectric hard mask layer 80 may be formed, for example, by CVD, PECVD or ALD. The thickness of the dielectric hard mask layer 80 can be from 10 nm to 50 nm, although lesser and greater thicknesses can also be employed.
The OPL 92 is formed on the dielectric hard mask layer 80 as a blanket layer. The OPL 92 may include an organic planarization material, which is a self-planarizing organic material that includes carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material can be a polymer with sufficiently low viscosity so that the top surface of the OPL 92 forms a planar horizontal surface. Exemplary organic planarization materials include, but are not limited to, near-frictionless carbon (NFC) material, diamond-like carbon, polyarylene ether, and polyimide. The OPL 92 can be deposited, for example, by spin coating. The thickness of the OPL 92 can be from 100 nm to 500 nm, although lesser and greater thicknesses can also be employed.
The antireflective hard mask layer 94 is formed on the OPL 92 as a blanket layer. The antireflective hard mask layer 94 may include an antireflective coating material as known in the art. The antireflective hard mask layer 94 is employed in the lithographic process to improve the photoresist profile and to reduce the line width variation caused by scattering and reflecting light. The antireflective hard mask layer 94 may include a silicon-containing antireflective coating (SiARC) material, a titanium-containing antireflective coating material (TiARC), silicon nitride, silicon oxide or TiN. In one embodiment, the antireflective hard mask layer 94 is composed of a SiARC material. The antireflective hard mask layer 94 can be applied, for example, by spin coating or CVD. The thickness of the antireflective hard mask layer 94 can be from 10 nm to 150 nm, although lesser and greater thicknesses can also be employed.
A photoresist layer (not shown) is deposited as a blanket layer atop the antireflective hard mask layer 94, for example, by spin coating. The photoresist layer may include any conventional organic photoresist material such as, for example, methacrylates or polyesters. The photoresist layer may have a thickness from 30 nm to 500 nm, although lesser and greater thicknesses can also be employed. The photoresist layer is then lithographically patterned into a predetermined shape forming the photoresist portion 96P atop the antireflective hard mask layer 94.
Referring to
Referring to
Subsequently, the metallic hard mask layer 70 is patterned using the OPL portion 92P as an etch mask. The patterning of the metallic hard mask layer 70 can include a dry etch such as, for example, RIE, plasma etch, or ion beam etch that removes the metal that provides the metallic hard mask layer 70 selective to the metal that provides the metal layer 60. In one embodiment, the metallic hard mask layer 70 can be etched with a RIE process employing chlorine (Cl2) gas or chlorine-containing gases as an etchant. After the etch, the remaining portion of the metallic hard mask layer 70 is herein referred to as a metallic hard mask portion 70P. In one embodiment and as shown in
The antireflective hard mask portion 94P is removed by the etch chemistries employed to etch the dielectric hard mask layer 80 and the metallic hard mask layer 70. Any OPL portion 92P remained after the dry etches can be subsequently, removed, for example, by plasma ashing.
Referring to
Referring to
After the etch, the remaining portion of the metal layer 60 is herein referred to as a metal portion 60P, and the remaining portion of the MIEC material layer 50 is herein referred to as a MIEC material portion 50P. In one embodiment and as shown in
Referring to
A MIEC-based memory cell access device for a memory cell is thus formed using a subtractive etch process. The MIEC-based memory cell access device includes a MIEC material portion 50P sandwiched between a bottom electrode 40 and a top electrode (60P or the combination of 60P and 70P). In the present application, since the MIEC material portion 50P is formed by a subtractive etch process, the contact area between the top electrode (60P or the combination of 60P and 70P) and the MIEC material portion 50P is substantially the same as the contact area between the bottom electrode 40 and the MIEC material portion 50P. That is, the contact area between the top electrode (60P or the combination of 60P and 70P) and the MIEC material portion 50P is no more than 20% greater than the contact area between the bottom electrode 40 and the MIEC material portion 50P. Due to the better symmetry with respect to the electrode contact areas, the resulting MIEC-based memory cell access device exhibits improved I-V characteristics and reduced low voltage leakage currents. In addition, since CMP process for the MIEC material is not needed in the subtractive etch process, surface defects caused by the CMP process can be eliminated. In the present application, the critical dimension (i.e., smallest allowable with) of the MIEC-based memory cell is defined by the lithograph tool. The subtractive etch process employed in the present application thus allows fabricating large numbers of devices for a given area.
Referring to
Referring to
Referring
Next, the processing steps described above in
A MIEC-based memory cell access device is thus formed. The MIEC-based memory cell access device includes vertically stacked MIEC material portions 50P sandwiched between a bottom electrode 40 and a top electrode. The vertically stacked MIED material portions 50P are separated from one another by metal portions 60P. In the second embodiment, the access device with vertically stacked MIEC material portions 50P exhibits a higher MIEC voltage margin than the access device with a single MIEC material portion 60P, which enables driving larger sizes of memory arrays. In addition, since the stack of alternating MIEC material layers 50 and metal layers 60 can be etched in a single etch step, no additional processing step is needed in the second embodiment compared to the first embodiment.
While the present application has been particularly shown and described with respect to various embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
