BACKGROUND
When designing switching circuits (e.g., power converters), parasitic loop inductance may be an important design parameter. High loop inductance may result in large voltage spikes during switch commutation, potentially resulting in increased switching loss and/or breakdown of a switch. There is a need for switching devices with a reduced loop inductance.
SUMMARY
The following is a short summary of some of the inventive concepts for illustrative purposes only and is not an extensive overview, and is not intended to identify key or critical elements or to limit or constrain the inventions and examples in the detailed description. One skilled in the art will recognize other novel combinations and features from the detailed description.
Described herein are methods, devices, and systems for providing an integrated switch device by integrating multiple switches on a single semi-conductive substrate according to a desired power conversion topology, in a manner designed to reduce loop inductance.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other features, aspects, and advantages of the present disclosure will become better understood with regard to the following description, claims, and drawings. The present disclosure is illustrated by way of example, and not limited by, the accompanying figures. In the drawings, like numerals reference similar elements.
FIG. 1A and FIG. 1B show an integrated switch arrangement according to one or more aspects of the disclosure herein.
FIG. 2 shows an integrated switch arrangement according to one or more aspects of the disclosure herein.
FIG. 3 shows a buck converter utilizing an integrated switch arrangement according to one or more aspects of the disclosure herein.
DETAILED DESCRIPTION
The accompanying drawings, which form a part hereof, show one or more examples of the disclosure. It is to be understood that the examples shown in the drawings and/or discussed herein are non-exclusive and that there are other examples of how the disclosure may be practiced.
Reference is made to FIG. 1A, which depicts integrated switch 100a in accordance with an aspect of the disclosure herein. Integrated switch 100a may include a source 105 disposed on a semi-conductive substrate 101 (e.g., on a source location and/or contact), drains D1 and D2 disposed on the semi-conductive substrate 101 (e.g., on first and second drain locations and/or contacts), and gates G1 and G2 disposed on the semi-conductive substrate 101 (e.g., on first and second gate locations and/or contacts). The semi-conductive substrate 101 may be a negative type (N-type) substrate or a positive type (P-type) substrate. Channel 102a may be formed between source 105 and drain D1, and channel 102b may be formed between source 105 and drain D2. According to some aspects, channels 102a and 102b may be formed as depletion mode channels. For example, when no voltage is applied between G1 and source 105, channel 102a may conduct, and when a voltage is applied between G1 and source 105, channel 102a may be depleted of charge carriers and no current may flow. For example, when no voltage is applied between G2 and source 105, channel 102b may conduct, and when a voltage is applied between G2 and source 105, channel 102b may be depleted of charge carriers and no current may flow.
Channels 102a and 102b may be disposed in close proximity to one another. For example, distance 103 between channels 102a and 102b may be less than 10 millimeters, 5 millimeters, 1 millimeter, or 0.1 millimeter. The close spatial proximity (e.g., less than a predetermined threshold length) may reduce a loop inductance formed when integrated switch 100a is used in a power circuit. A capacitance (not shown in the figure) may be formed by the spatial proximity (e.g., close spatial proximity) between channels 102a and 102b.
In some aspects of the disclosure, a trench 104 may be formed between channel 102a and channel 102b. The trench may be formed at the close spatial proximity between the channels 102a and 102b. Therefore, the width of the trench 104 may be narrow and less than the distance 103 between channels 102a and 102b.
In some aspects of the disclosure, a controller may be configured to apply a first voltage signal to gate G1 and a second voltage signal to gate G2. The second voltage signal may be complementary to the first voltage signal. For example, the controller (e.g., gate-driver, microcontroller, field-programmable gate array (FPGA), etc.) may be configured to apply a first voltage signal characterized by a switching frequency having a duty cycle of D to gate G1 and a second voltage signal characterized by the switching frequency having a duty cycle of (1−D) to gate G2.
Reference is now made to FIG. 1B. Integrated switch 100b is similar to integrated switch 100a but does not include a trench. In integrated switch 100b, two gates (e.g., contacts of gates) of the same type may be placed on either side of each channel. For example, two G1 gates (e.g., contacts of G1 gates), connected in parallel, may be placed on both sides of channel 102a (e.g., a first G1 gate contact on the left side of channel 102a and a second G1 gate contact on the right side of channel 102a) and two G2 gates (e.g., contacts of G2 gates), connected in parallel, may be placed on both sides of channel 102b (e.g., a first G2 gate contact on the left side of channel 102b and a second G2 gate contact on the right side of channel 102b). A contact may be also referred to as an electrode.
Reference is now made to FIG. 2, which depicts integrated switch 200 in accordance with aspects of the disclosure herein. Integrated switch 200 may be similar to integrated switches 100a and 100b (e.g., with channels as depletion mode channels), but with additional gates (e.g., contacts of gates) (collectively, G1 in FIG. 2) connected in parallel to first gate G1 of FIG. 1A, additional drains (e.g., contacts of drains) (collectively, D1 in FIG. 2) connected in parallel to drain D1 of FIG. 1A, and additional channels between each gate and drain. The same may hold for additional second gates, drains and channels. For example, additional gates (e.g., contacts of gates) (collectively, G2 in FIG. 2) may be connected in parallel to second gate G2 of FIG. 1A, additional drains (e.g., contacts of drains) (collectively, D2 in FIG. 2) may be connected in parallel to drain D2 of FIG. 1A, and additional channels may be formed between each gate and drain. Increasing the numbers of parallel-connected gates and drains and providing corresponding channels may reduce a resistance of the integrated switch and may further reduce loop inductance by spatially interleaving the currents flowing in each channel. The gate-channel-drain cells may be vertically stacked. In some aspects of the disclosure, a trench (e.g., an optional trench) may be formed between at least one pair of adjacent channels (e.g., channel 102a and channel 102b of FIG. 1A). The trench may be formed between the gates (e.g., contacts of gates, such as first gate G1 and second gate G2). The source may be common to all the additional channels between each gate and drain.
Reference is now made to FIG. 3, which shows an example for integrated switch 301 used as part of a power converter 300. Integrated switch 301 may comprise one or more of integrated switches 100a, 100b, and 200 of FIGS. 1A, 1B, and 2, respectively. Power converter 300 may be a buck converter utilizing integrated switch 301 as a half-bridge stage of the buck converter. Integrated switch 301 may be the same as or similar to one or more of integrated switches 100a, 100b, and 200. Terminals of drains D1 and D2 may be connected across direct current (DC) voltage terminals of power source 303. A source terminal may be connected to inductor L1, and a voltage Vout may be provided at a connection point between inductor L1 and capacitor C1. Controller 302 may provide signals to terminals respectively connected to gates G1 and G2 of integrated switch 301. When a voltage (e.g., a voltage above a threshold voltage) is applied to gate G1, channel(s) between first drain D1 and the source may be depleted of charge carriers, and current may flow between second drain D2 and the source. When a voltage (e.g., a voltage above a threshold voltage) is applied to gate G2, channel(s) between second drain D2 and the source may be depleted of charge carriers, and current may flow between first drain D1 and the source. Controller 302 may be configured to provide complementary signals to gates G1, G2. For example, controller 302 may provide a pulse-width modulation (PWM) signal having a duty cycle of 0.7 to gate G2, and a PWM signal having a duty cycle of 1−0.7=0.3 to gate G1, which may result in a voltage conversion ratio of 70% (e.g., since current flows between second drain D2 and the source 70% of the time). Controller 302 may comprise one or more digital and/or analog control circuits. Controller 302 may include, for example, one or more processors (e.g., a central processing unit (CPU), a microprocessor, an FPGA, etc.), memory (e.g., random access memory, read-only memory, flash memory, etc.), etc.
Integrated switches 100a, 100b, and/or 200 may be variously configured in different power topologies. For example, integrated switches 100a, 100b, and/or 200 may be used in buck converters, boost converters, buck-boost converters, full-bridge direct current/alternate current (DC/AC) or AC/DC converter, and the like.
All described features, and modifications of the described features, are usable in all aspects of the inventions taught herein. Furthermore, all of the features, and all of the modifications of the features, of all of the embodiments described herein, are combinable and interchangeable with one another