Number | Date | Country | Kind |
---|---|---|---|
11-230702 | Aug 1999 | JP | |
12-244839 | Aug 2000 | JP |
Number | Name | Date | Kind |
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5900752 | Mar | May 1999 |
Entry |
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Takanori Saeki, et al, “A 10ps Jitter 2 Clock Cycle Lock Time CMOS Digital Clock Generator Based on an Interleaved Synchronous Mirror Delay Scheme”, Symposium on VLSI Circuits Digest of Technical Papers, pp. 109-110, Jun. 1999. |