“A Sub-10nS Cache SRAM for High Performance 32 bit Microprocessors”, Ed Reese and Eddy Haung, IEEE Custom Integrated Circuits Conference, 1990, pp. 24.2.1-24.2.4. |
A 20 ns 246K αFIFO Memory, Masashi Hashimoto, et al., Proceedings of the IEEE Custom Integrated Circuits Conference, 05/87, pp. 315-318. |
“A 20-ns 256K αFIFO Memory”, Masashi Hashimoto, et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 2, 04/88, pp. 490-499. |
“55 NS, 1.3 MB Video Memory With Rectangular Access for Graphic Systems”, Toshiki Mori, et al., Electronic Information Comm. Institute Technological Research Report, vol. 89, No. 69, 06/89, pp. 1-17. |
“Internally time RAMs build fast writable control stores”, Mohammad Shakalb Iqbal, Fujitsu Microelectronics, Inc., Electronic Design Applications, Increase memory speed, 08/88, pp. 93-96. |
“Motorola's Radical SRAM Design Speeds Systems 40%”, Bernard C. Cole, Electronics, Technology to Watch, 07/87, pp. 66-68. |
“Self-Timed SRAMs Pace High-Speed ECL Processors”, Charles Hochstedler, High Speed Design, Semiconductor Memories, 1990, pp. 4, 5, 8, 10. |
“Special-feature SRAMs”, John Gallant, Associate Editor, EDN Special Report, 06/91, pp. 105-110, 112. |
Specialty SRAMs are Filling the Speed Gap, Samuel Weber, Electronics, 05/90, pp. 85-87. |
“SRAMs' on-chip address and data latches boost throughout in pipelined systems”, Steven H. Leibson, EDN, Product Update, Circle No. 726, 10/88, pp. 102, pp. 104. |
Static RAMs have on-chip addres and data latches for pipelining, Integrated Circuits, EDN, Circle No. 569, 12/88, pp. 116. |
“System Snags Shouldn't Slow the Boom in Fast Static RAMS”, J. Robert Lineback, Electronics, Inside Technology, 07/87, pp. 60-62. |
“Will the search for the ideal memory architecture ever end?”, Ron Wilson, Computer Design, 07/90, pp. 78-84, pp. 88, pp. 90. |