System and method for acceleration of streams of dependent instructions within a microprocessor

Abstract

A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

The accompanying drawings, which are incorporated herein and form part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.

FIG. 1 depicts a prior art implementation for sequential processing of instructions consisting of an arithmetic logic unit (ALU) within a pipeline in a processor.

FIG. 2 depicts a system view of a sequential accelerator system within a pipeline in a processor, as well as a supporting configuration memory, in accordance with an embodiment of the present invention.

FIG. 3 illustrates a flow chart of a sequential accelerator system describing the setup and execution of a configuration used by the sequential accelerator in accordance with an embodiment of the present invention.

FIG. 4 depicts an instruction format used by a sequential accelerator system in accordance with an embodiment of the present invention.

FIG. 5 depicts a similar system view to FIG. 2, but further illustrates the contents of the configuration memory and how information flows between the various components, in accordance with an embodiment of the present invention.

Claims

1. A method for processing instructions in an integrated circuit (IC) chip comprising a processor and a sequential accelerator, the method comprising: storing one or more operations to be processed by the sequential accelerator;receiving and processing a first instruction in the processor; andresponsive to the processing of the first instruction by the processor:processing the one or more operations in the sequential accelerator, andproviding the results of the one or more operations in the sequential accelerator to the processor.

2. The method of claim 1, wherein the step of storing the one or more operations is performed responsive to the processing of a second instruction by the processor.

3. The method of claim 2, wherein the step of processing the second instruction in the processor comprises: storing data to be used by the sequential accelerator when processing the one or more operations, wherein the data is included with the second instruction.

4. The method of claim 1, wherein the step of processing the first instruction in the processor comprises: decoding the first instruction to identify the one or more operations to be processed by the sequential accelerator.

5. The method of claim 1, wherein the step of processing the one or more operations in the sequential accelerator further comprises: processing the one or more operations asynchronously relative to the processor.

6. The method of claim 1, wherein the step of processing the one or more operations in the sequential accelerator further comprises: processing the one or more operations at a multiple clock rate relative to the processor.

7. The method of claim 1, further comprising: receiving additional instructions in the processor; andcontinuing processing of the additional instructions in the processor without waiting for the sequential accelerator to finish processing the one or more operations.

8. The method of claim 1, wherein the step of processing the one or more operations in the sequential accelerator further comprises: determining whether each of the one or more operations is predicated;processing each of the one or more operations that is predicated only if a flag is set; andprocessing each of the one or more operations that is not predicated.

9. An integrated circuit for processing sequential instructions, the IC comprising: a processor; anda sequential accelerator;wherein the processor is configured to transfer to the sequential accelerator one or more operations to be processed by the sequential accelerator when the processor executes an instruction triggering processing by the sequential accelerator of the one or more operations.

10. The integrated circuit of claim 9, further comprising: a first memory location, wherein the first memory location contains one or more constant information fields;wherein the constant information fields are accessible by the processor and by the sequential accelerator, andwherein the constant information fields are set by the processor.

11. The integrated circuit of claim 9, further comprising: a second memory location, wherein the second memory location contains one or more result fields;wherein the sequential accelerator is configured to store information in the one or more result fields, andwherein the processor is configured to read information from the one or more result fields.

12. The integrated circuit of claim 9, further comprising: a third memory location, wherein the third memory location contains one or more configuration fields;wherein the processor writes to each of the one or more configuration fields the one or more operations to be processed by the sequential accelerator responsive to one or more instructions, andwherein the processor reads from each of the one or more configuration fields the one or more operations to be processed by the sequential accelerator in order to transfer the one or more operations to the sequential accelerator.

13. The integrated circuit of claim 9, further comprising: one or more internal registers, located within the sequential accelerator;wherein the one or more internal registers are used by the sequential accelerator for performing its processing procedures, andwherein the one or more internal registers are not accessible by the processor.

14. The integrated circuit of claim 9, further comprising: a pipeline, located within the processor, the pipeline for processing instructions in stages.

15. The integrated circuit of claim 14, further comprising: a pipeline decode stage, within the pipeline, wherein the pipeline decode stage determines if an instruction within the pipeline decode stage is to trigger the processing of the one or more operations by the sequential accelerator;wherein if the instruction within the pipeline decode stage is to trigger the processing of the one or more operations by the sequential accelerator, the one or more operations are sent to the sequential accelerator for processing,wherein if the instruction is to trigger the processing of the one or more operations by the sequential accelerator, it is removed from the pipeline, andwherein the processor continues to process instructions regardless of whether the sequential accelerator is currently processing the one or more operations.

16. The integrated circuit of claim 9, further comprising: one or more parallel pipelines, within the sequential accelerator, the one or more parallel pipelines for processing the one or more operations concurrently.

17. A pipeline located within a processor, the pipeline comprising: an instruction decode stage; andan instruction configuration path, the instruction configuration path for configuring a sequential accelerator to process an operation;wherein if the instruction decode stage receives an instruction requesting the configuration of the sequential accelerator to process the operation, the instruction decode stage decodes the instruction to determine the operation to be processed by the sequential accelerator and triggers the configuration of the sequential accelerator, using the instruction configuration path, to enable it to process the operation.

18. The pipeline of claim 17, further comprising: a configuration memory, wherein the configuration memory contains one or more operations in a form that is interpretable by the sequential accelerator, such that an instruction requesting the configuration of the sequential accelerator to process one or more of the one or more operations is associated with one or more of the one or more operations.