Patent Application
20050160238
Multi-processor systems employ two or more computer processors that can communicate with each other, such as over a bus or a general interconnect network. In such systems, each processor may have its own memory cache (or cache store) that is separate from the main system memory that the individual processors can access. Cache memory connected to each processor of the computer system can often enable fast access to data. Caches are useful because they tend to reduce latency associated with accessing data on cache hits, and they work to reduce the number of requests to system memory. In particular, a write-back cache enables a processor to write changes to data in the cache without simultaneously updating the contents of memory. Modified data can be written back to memory at a later time.
Coherency protocols have been developed to ensure that whenever a processor reads a memory location, the processor receives the correct or true data. Additionally, coherency protocols help ensure that the system state remains deterministic by providing rules to enable only one processor to modify any part of the data at any one time. If proper coherency protocols are not implemented, however, inconsistent copies of data can be generated.
There are two main types of cache coherency protocols, namely, a directory-based coherency protocol and a broadcast-based coherency protocol. A directory-based coherency protocol associates tags with each memory line. The tags can contain state information that indicates the ownership or usage of the memory line. The state information provides a means to track how a memory line is shared. Examples of the usage information can be whether the memory line is cached exclusively in a particular processor's cache, whether the memory line is shared by a number of processors, or whether the memory line is currently cached by any processor.
A broadcast-based coherency protocol employs no tags. Instead, in a broadcast-based coherency protocol, each of the caches monitors (or snoops) requests to the system. The other caches respond by indicating whether a copy of the requested data is stored in the respective caches. Thus, correct ownership and usage of the data are determined by the collective responses to the snoops.
One embodiment of the present invention may comprise a system that includes a first node that provides a source broadcast request for data. The first node is operable to respond in a first manner to other source broadcast requests for the data while the source broadcast request for the data is pending at the first node. The first node is operable to respond in a second manner to the other source broadcast requests for the data in response to receiving an ownership data response at the first node.
Another embodiment of the present invention may comprise a multi-processor network that includes a source processor node that provides a source broadcast read request for data. The source processor node issues an invalidate line command to other processor nodes of the system in response to receiving a data response that transfers a cache ordering point for the data to the source processor node.
Another embodiment of the present invention may comprise a method that includes migrating a cache ordering point for a line of data from a second node of a system to a first node of a system. The method also includes issuing an invalidate line command for the line of data to other nodes of the system in response to receiving a conflict response from at least one other node in the system and to the cache ordering point migrating from the first node to the second node.
Yet another embodiment of the present invention may comprise a method including providing from a first node a first conflict response to source broadcast requests for data from other nodes while a source broadcast for the data is pending at the first node. The method may also include providing from the first node a second conflict response to the other source broadcast requests for the data from the other nodes in response to receiving a conflict response and an ownership data response at the first node.
Still another embodiment of the present invention may comprise a computer system that includes a plurality of nodes. The plurality of nodes employ a cache coherency protocol operative to migrate a cache ordering point for a line of data from a target node to a source node in response to a source broadcast read request for the line of data issued by the source node. The source node is operative to invalidate the line of data at other nodes of the computer system in response to receiving a conflict response and migratory data to the source broadcast read request.
This disclosure relates generally to systems and methods for conflict responses in a cache coherency protocol that supports migratory data. Migratory Data can be defined as a class of memory blocks that are shared by a plurality of processors and are characterized by a per processor reference pattern which includes a read and a write in close temporal proximity in the instruction stream of the processor. In general, such data blocks are expected to be shared in a manner in which each processor is provided with an opportunity to complete its read-write sequence before any other processors initiate their read-write sequence.
The per processor read-write sequence associated with Migratory Data can manifest itself in the system as a two-step per processor sequence consisting of a simple data read request (XREAD) followed by an upgrade (XUPGRADE) reference to make the line writable. An optimization is to reduce this two-step per processor sequence to a single step by implementing a single “Read with Modify Intent” (XRDINVAL) request. Implementation of the single XRDINVAL request greatly reduces the latency of the request and reduces system request traffic. The cache coherency protocol described herein provides this optimized migratory data support through implementation of the XRDINVAL request.
Migratory data support is a system function implemented through the cache coherency protocol described herein. When a processor begins a migratory data sequence, it encounters a read reference in its instruction stream that provides no indication that the read reference is operative on a migratory data line. Thus, when the read request is issued to the system by the processor, it is issued as a simple read request (XREAD). The cache coherency protocol described herein employs a predictive function to determine whether the read request is addressing a migratory data line. This predictive function can be a cache state decoding mechanism responsive to the states of all processors that are targets of snoops associated with the XREAD request. The predictive function implemented in the cache coherency protocol described herein covers a comprehensive set of coherence timing and conflict cases that can arise in during migratory data flows. Once migratory data is detected, the XREAD request is completed implementing measures to ensure that the XREAD is completed correctly.
The cache coherency protocol described herein supports migratory read commands by employing cache states (described in detail below) that function to predict whether a read command, or read snoop, involves migratory data. If a read snoop finds the requested line cached in a modified state in another cache, the data is returned to the requestor in a dirty state. Thus, in effect, when migration takes place, the migratory read command acts like a write command, moving the cache ordering point to the requesting node.
The cache coherency protocol employs conflict states that are assigned to a miss address file (MAF) entry for an outstanding broadcast snoop request. The conflict states are used to determine how to handle conflicts between MAFs that are associated with the same cache line and that are valid and/or active at the same time. The conflict states can include a read conflict (RD-CONF) state and a conflict (CONFLICT) state. In general, the RD-CONF state is assigned to a MAF entry in a conflict scenario in which migratory data has not been detected. In general, the CONFLICT state is assigned to a MAF entry in a conflict scenario in which migratory data has been detected.
The implementation of the CONFLICT and RD-CONF states can also be utilized in multi-processor systems employing a hybrid cache coherency protocol, such as the SSP/FPP hybrid cache coherency protocol described herein. In a conflict scenario in which a source processor receives a data response and a RD-CONF response to a broadcast snoop request for data, the source processor can place the data in a cache associated with the source processor. In a conflict scenario in which a source processor receives a data response and a CONFLICT response to a broadcast snoop request for data, the source processor can employ a forward progress technique to complete the request. For example, the source processor can transition to a forward progress protocol (FPP) mode and reissue the request for the data using FPP request commands. Other forward progress techniques could also be utilized. The cache coherency protocol disclosed herein thus mitigates having to transition to the FPP mode in certain conflict scenarios, which can help reduce latency.
Since migratory reads begin as simple read requests (XREAD), there can be a substantial period of time between the time a MAF for an XREAD request is created and the time when the source processor knows that the read is migratory. Prior to receiving indication that the read is migratory, the source node can respond to snoop requests from other nodes requesting the same line by providing a RD-CONF response. This can be problematic since these other processors may end up consuming stale data once the data migrates to the source processor. The cache coherency protocol described herein takes this into account by employing a migratory mode at the source processor once migration of the cache ordering point has begun. The migratory mode helps ensure correctness of the transaction, e.g., that the migratory data migrates to the source processor and that other processors requesting the same line do not consume stale data. In the migratory mode, the source processor responds to snoops for the same line from other nodes with the CONFLICT response and invalidates the line for other processors that may have received stale or incorrect data. The migratory mode will be discussed in greater detail below.
The processors 12 and 14 and memory 16 define nodes in the system that can communicate with each other via requests and corresponding responses through a system interconnect 18. For example, the system interconnect 18 can be implemented as a switch fabric or a hierarchical switch. Also associated with the system 10 can be one or more other nodes, indicated schematically at 20. The other nodes 20 can correspond to one or more other multi-processor systems connected to the system interconnect 18, such as through an appropriate interconnect interface (not shown).
Each of the processors 12 and 14 includes at least one corresponding cache 22 and 24. For purposes of brevity, each of the respective caches 22 and 24 is depicted as unitary memory devices, although the caches may include a plurality of memory devices or different cache levels. Each of the caches 22 and 24 includes a plurality of cache lines. Each cache line has an associated tag address that identifies corresponding data stored in the line. The cache lines can also include information identifying the state of the data for the respective lines.
The system 10 thus employs the caches 22 and 24 and the memory 16 to store blocks of data, referred to herein as “memory blocks.” A memory block can occupy part of a memory line, an entire memory line or span across multiple lines. For purposes of simplicity of explanation, however, it will be assumed that a memory block occupies a single “memory line” in memory or a “cache line” in a cache. Additionally, a given memory block can be stored in a cache line of one or more caches as well as in a memory line of the memory 16.
Each cache line can also include information identifying the state of the data stored in the respective cache. A given memory block can be stored in a cache line of one or more of the caches 22 and 24 as well as in a memory line of the memory 16, depending on the state of the line. Whether a cache line contains a coherent copy of the data also depends on the state of the cache line. Certain states employed by the coherency protocol can define a given cache line as an ordering point for the system 10 employing a broadcast-based protocol. An ordering point characterizes a serialization of requests to the same memory line (or memory block) that is understood and followed by the system 10.
The system 10 implements the cache coherency protocol to manage the sharing of memory blocks so as to help ensure coherence of data. The cache coherency protocol of the system 10 utilizes a plurality of states to identify the state of each memory block stored in respective cache lines of the caches 22 and 24 and the memory 16. The coherency protocol establishes rules for transitioning between states, such as if data is read from or written to memory 16 or one of the caches 22 and 24.
The coherency protocol can be implemented as a hybrid cache coherency protocol, such as a broadcast source snoop protocol (SSP) implemented in conjunction with a forward progress (e.g., directory-based or null-directory) protocol (FPP). Characteristic of the hybrid cache coherency protocol, requests for data are initially transmitted broadcast using SSP broadcast snoop requests. If the snoop requests fail or otherwise cannot be completed, such as where there is a conflict between multiple processors attempting to read and/or write the same cache line, the protocol can transition to the FPP mode and the requests can be reissued using FPP request commands. Other forward progress techniques could also be utilized.
As used herein, a node that issues a request, such as a read or write request, defines a source node. Other nodes within the system 10 are potential targets of the request. Additionally, each memory block in the system 10 can be assigned a home node that maintains necessary global information and a data value for that memory block. When a source node issues a source broadcast snoop request for data, an entry associated with the request is allocated in a miss address file (MAF). The MAF maintains information associated with, for example, the address of the data being requested, the type of request, and response information received from other nodes in response to the request. The MAF entry for the request is maintained until the request associated with the MAF is complete.
For example, when a source node, such as the processor 12, requires a copy of a given memory block, the source node typically first requests the memory block from its local, private cache by comparing selected cache tags to the address associated with the memory block. If the data is found locally, the memory access is resolved without communication via the system interconnect 18. When the requested memory block is not found locally, the source node 12 can request the memory block from the system 10, including the memory 16. In addition to the request identifying an address associated with the requested memory block, the request usually identifies the type of request or command being issued by the requester. Whether the other nodes 14 and the memory 16 will return a response depends upon the type of request, as well as the state of the identified memory block if contained in the responding nodes. The cache coherency protocol implemented by the system 10 defines the available states and possible state transitions.
A set of cache states that can be included in the cache coherency protocol described herein is depicted below in Table 1. Each cache line of the respective caches 22 and 24 of the processors 12 and 14 may be associated or tagged with one of the cache states in table 1. Since there are eight possible states, the state information can be encoded by a three-bit data word, for example.
As mentioned above, the state of a cache line can be utilized to define a cache ordering point in the system 10. In particular, for a protocol implementing the states set forth in Table 1, a processor including a cache line having one of the states M, O, E, F or D may be referred to as an owner processor or node and can serve as a cache ordering point for the data contained in the cache line for transactions in the broadcast-based protocol. An owner processor (e.g., processor 12 or 14) that serves as the cache ordering point is capable of responding with data to snoops for the data. For example, processor 14 may be an owner processor for particular data and thus can provide a copy of the data to another cache 12. The type of data returned by an owner processor depends on the state of the data stored in the processor's cache. The response may also vary based on the type of request as well as whether a conflict exists. The memory 16 seeks to return a copy of the data stored in the memory. The memory copy of the data is not always a coherent copy and may be stale (e.g., when there is a modified copy of the data cached by another processor).
The cache coherency protocol described herein provides for ordering point migration in which a cache ordering point is transferred from cache of a target processor to cache of a source processor in response to a source broadcast read request depending on a migratory predictor, such as the cache state of a target processor for a line of data. For example, a target node (e.g., processor 14) including an M-state cache line can, in response to a source broadcast read request, provide an ownership data response to a source node (e.g., processor 12), and the source node cache line transitions to the D-state. Upon completion of the ordering point transfer, the target processor 14 cache line transitions to the I-state. The ordering point is thus transferred (i.e., the ordering point migrates) from the target processor 14 to the source processor 12.
To mitigate the vulnerability of the ordering point during migration, the cache line of the target processor 14 can transition to the T-state while the ordering point migration is pending. Additionally, the source processor 12 can provide a message that acknowledges when the ordering point has successfully migrated (e.g., a migration acknowledgement or “MACK” message). The cache line of the target processor 14 can further transition from the T-state to the I-state in response to receiving the MACK message from the source processor 12. The target processor 14 can respond to the MACK message by providing a further acknowledgement message back to the source processor 12 (e.g., a MACK acknowledgement or MACK-ACK message). The source broadcast read request by the source processor 12 that initiated the migration sequence can be considered completed in response to receiving the MACK-ACK message from the target processor 14.
The processors 12 and 14 of the system 10 can obtain copies of desired data by issuing data requests in either the SSP or FPP portion of the cache coherency protocol implemented in the system. A list of example data requests that can be included in the SSP portion of the cache coherency protocol described herein, and thus issued through a source broadcast request by a processor (e.g., processors 12 and 14), is depicted below in Table 2.
According to the cache coherency protocol described herein, source processors 12 and 14 issue data requests initially as broadcast snoop requests using the SSP commands set forth in Table 2. If the snoop requests fail and a transition to the FPP is required (e.g., due to a conflict), the system 10 can reissue the request using a forward progress technique. For example, the system 10 can transition to an FPP mode and the requests can be reissued using FPP commands.
Whenever a broadcast read or write snoop is issued by a source node (e.g., source processor 12) in the system 10, target nodes of the system (e.g., target processor 14, memory 16, and nodes 20) may issue an SSP response to the snoop. A list of example SSP responses that may be included in the cache coherency protocol described herein is depicted below in Table 3.
When a source node (e.g., source processor 12) issues a source broadcast request for data, each of the target nodes (e.g., target processor 14, memory 16, and nodes 20) having a copy of the requested data may provide a data response. In the cache coherency protocol described herein, there are three different types of data responses: shared data responses (S-DATA), dirty data responses (D-DATA), and memory data responses (M-DATA). It is thus possible that, in response to a source broadcast request for data, the source processor 12 can receive several different data responses. Accordingly, the source processor 12 requester can employ a data state machine associated with the MAF entry for the source broadcast request to manage filling data in the cache of the source processor.
A target node can provide an ownership data response that includes D-DATA, for example, when the processor has an ownership state (e.g., M, O, E, F or D) associated with the cached data in the SSP protocol. It is the state of the cached data that defines the node (processor) as a cache ordering point for the data. When a processor responds with D-DATA, the ordering point is transferred to the requesting processor. S-DATA is a shared data response that indicates data is being returned from a cache ordering point, although the ordering point itself is not being transferred to the requester. An S-DATA response also indicates that a copy of the data may be in one or more other caches. An M-DATA response can be provided by memory (e.g., a home node) by returning the present value for the data stored in memory. It is possible that the M-DATA is stale and not up-to-date.
Examples of processor snoop responses to source broadcast snoop requests that can occur in the system 10 and the target node state transitions that result therefrom are provided in Table 4. The state transitions set forth in Table 4 assume that no conflicts are encountered in response to the respective commands. Conflict conditions can affect state transitions, as described herein. As shown in Table 4, the response to the source node varies depending on the type of broadcast snoop request received at the target node and the cache state of the target node when the snoop request is received.
Referring to Table 4 and
In a conflict state machine (see, e.g.,
One type of conflict situation can occur when two or more processors each have an outstanding request for the same line of data and a MAF associated with their respective requests. The response issued by a responding target processor of the group of conflicting processors depends on the MAF state for the conflicting request of the responding target processor. A list of example target processor responses that may be issued in conflict cases according to the cache coherency protocol described herein is depicted below in Table 5.
*DSM = Data State Machine (See
As shown in Table 5, if a target node has an outstanding MAF in any FPP request state except a victim request when the source broadcast read or write request is received, the target node issues an FPP response to the source node and the target node MAF state remains unchanged. If a target node has an outstanding MAF in a FPP victim request state when the source broadcast read or write request is received, the target node issues a CONFLICT response to the source node and the target node MAF state remains unchanged. Also, if a target node has an outstanding MAF in one of the broadcast read states set forth in Table 5 when the source broadcast read or write request is received, the target node issues a RD-CONF response to the source node and the target node MAF state transitions according to the conflict state machine (see, e.g.,
After all target nodes have responded to a source broadcast read/write request issued by a source node, the action taken at the source node proceeds according to several factors. These factors include the type of source broadcast read/write request issued by the source node, the resulting state of the data state machine (see, e.g.,
Referring back to
According to the cache coherency protocol described herein, an example sequence of events for an XREADN transaction is as follows:
The source processor 12 may also transmit a source broadcast read snoop (XREAD, see, e.g., Table 2) to the other processor 14, to the memory 16, and to the other nodes 20 via the system interconnect 18. The other nodes in the system respond to the XREAD request by providing either a data response or a non-data response (see, e.g., Table 3), depending on factors such as the state of the respective nodes when the request is received and whether there is a conflict with the request, as described herein. The responses drive the data state machine and conflict state machine associated with the XREAD request, as described herein. After all responses to the XREAD request have returned from the nodes in the system 10, the resulting action taken at the source processor 12 is determined in accordance with the resulting data state/conflict state combinations, such as set forth below in Table 7.
According to the cache coherency protocol described herein, an example sequence of events for an XREAD transaction is as follows:
According to the cache coherency protocol described herein, a D-DATA response is predictive or indicative of migratory data. A CONFLICT or RD-CONF response from a target node indicates that a stale or incorrect M-DATA response provided by an owner node may have been consumed at the target node and, therefore, clean-up is required. Thus, as shown in Table 7, the source processor 12 enters the migratory mode when the MAF for the XREAD request has a D-DATA state for the associated data state machine and a conflict (CONFLICT or RD-CONFLICT) for the associated conflict state machine. In the migratory mode, the source processor 12 issues an XINVAL command to all of the other processors 14 and 20 in the system 10, except the owner processor. This eliminates any misleading RD-CONF states at the other processors 14 and 20 by invalidating any stale or incorrect data that may have been filled in the other processors after migration of the data to the source processor 12 was initiated. While migration is pending at the source processor 12, the source processor responds to any third party snoop requests with a CONFLICT response. Once the source processor 12 receives acknowledgment of the XINVAL commands issued to the other processors 14 and 20, the source processor issues a MACK message to the owner processor to acknowledge receipt of the migratory data. Upon receiving the MACK message from the source processor 12, the owner processor issues a MACK-ACK message to the source processor, and migration of the data is complete.
The source processor 12 may also transmit a source broadcast read current snoop (XREADC, see Table 2) to the other processor 14, to the memory 16, and to the other nodes 20 via the system interconnect 18. The other nodes in the system 10 respond to the XREADC request by providing either a data response or a non-data response (see Table 3), depending on factors such as the state of the respective nodes when the request is received and whether there is a conflict with the request, as described herein. The responses drive the data state machine and conflict state machine at the source processor 12 associated with the XREADC request, as described herein. After all responses to the XREADC request have returned from the nodes in the system 10, the resulting action taken at the source processor 12 is determined in accordance with the resulting data state/conflict state combinations, as set forth below in Table 8.
According to the cache coherency protocol described herein, an example sequence of events for an XREADC transaction is as follows:
The source processor 12 may also transmit a source broadcast read and invalidate line with owner snoop (XRDINVAL, see, e.g., Table 2) to the other processor 14, to the memory 16, and to the other nodes 20 via the system interconnect 18. As mentioned above, the XRDINVAL serves as a “read with modify intent” request. The other nodes in the system respond to the XRDINVAL request by providing either a data response or a non-data response (see, e.g., Table 3), depending on factors such as the state of the respective nodes when the request is received and whether there is a conflict with the request, as described herein. The responses drive the data state machine and conflict state machine associated with the XRDINVAL request, as described herein. After all responses to the XRDINVAL request have returned from the nodes in the system 10, the resulting action taken at the source processor 12 is determined in accordance with the resulting data state/conflict state combinations, as set forth below in Table 9.
According to the cache coherency protocol described herein, an example sequence of events for an XRDINVAL transaction are as follows:
The source processor 12 may also transmit a source broadcast upgrade/invalidate line snoop (XUPGRADE, see, e.g., Table 2) to the other processor 14, to the memory 16, and to the other nodes 20 via the system interconnect 18. The other nodes in the system respond to the XUPGRADE request by providing a non-data response (see, e.g., Table 3), depending on factors such as the state of the respective nodes when the request is received and whether there is a conflict with the request, as described herein. The responses drive the data state machine and conflict state machine associated with the XUPGRADE request, as described herein. After all responses to the XUPGRADE request have returned from the nodes in the system 10, the resulting action taken at the source processor 12 is determined in accordance with the resulting data state/conflict state combinations, such as set forth below in Table 10.
According to the cache coherency protocol described herein, an example sequence of events for an XUPGRADE transaction is as follows:
By way of further example, with reference to
In this example, it is assumed that, at the time of the XREAD request, at least one other processor (e.g., processor 14) in the system 10 has an outstanding XREAD request for the same data for which the owner node 20 has not yet responded. It is further assumed that yet another processor (e.g., one of the other nodes 20) is an owner node, i.e., a cache ordering point for the data. For this example, assume that the owner node 20 has a copy of the data in an M-state cache line of the owner node.
Upon receiving the XREAD request broadcast from the source processor 12, the memory will return an M-DATA response and the owner node 20 will identify the XREAD as a migratory request based upon its own M-state cache line. In response, the owner node 20 will return D-Data to the source processor 12 and transition to the T-state (see, e.g., Table 3). In response to receiving the XREAD request broadcast from the source processor 12, target processor 14 will return a RD-CONF response because target processor 14 has not yet received a D-DATA response from owner node 20, i.e., migration has not yet begun to target processor 14 (see, e.g., Table 5).
Referring to the data state diagram of
Referring to Table 7, the data state machine, being in the D-DATA state, indicates to the source processor 12 that the data line was identified as migratory and, thus, the source processor 12 should follow a migratory data control flow in completing the XREAD transaction. The conflict state machine, being in the RD-CONF state, indicates that there may be a misleading conflict state at other processors, e.g., one of the other nodes 20, that requires correction. The resulting action taken at the source node 12 is to fill the source node cache with the D-DATA and transition the source node cache line associated with the data to the D-state. The source node 12 then transitions to the migratory mode and broadcasts an XINVAL command to all other processors 20 (except the target node 14) to correct any incorrect or stale data that may have been filled at the other nodes 20. While the XINVAL is pending, the source node 12 responds to any third party snoops with CONFLICT responses instead of RD-CONF responses as set forth in the “Broadcast Writes” entry of Table 5. When all XINVAL acknowledgement responses have been received, the source node 12 initiates an MACK/MACK-ACK sequence with the target processor 14 to complete the ordering point migration. Thus, in this conflicting read scenario involving migratory data, according to the cache coherency protocol described herein, the data migrates from the target processor 14 to the source processor 12 and takes steps to correct any incorrect or stale data that may have been filled in the other nodes 20.
The above example illustrates a conflict scenario that leads to one of the data state/conflict state combinations of Table 7. It will be appreciated that the other data state/conflict state combinations of Table 7 would similarly result in the corresponding source node actions illustrated in Table 7. It will also be appreciated that the various data state and conflict state combinations of Table 7 may arise in a great number of circumstances involving conflict and non-conflict scenarios. Regardless of the scenario under which these data state/conflict state combinations are achieved, the action taken at the source node will be determined according to the data state/conflict state combination when all responses are received at the source node.
For example, if the data state machine indicates NO-DATA after all snoop responses have been received, the request can be reissued in the FPP mode, as set forth in Table 7. As another example, if the conflict state machine indicates FPP and the data state machine indicates S-DATA or M-DATA, the request can be reissued in the FPP mode, as set forth in Table 7. As a further example, if the conflict state machine indicates FPP and the data state machine indicates D-DATA, the source node cache is filled with the D-DATA and transitions to the O-state. Thereafter, the source node transitions to a migratory mode, in which the node broadcasts an XINVAL that invalidates the cache line associated with the data at the other nodes. After the XINVAL is acknowledged by the other processors, an MACK/MACK-ACK sequence is initiated and, when completed, the source node transitions to the FPP mode and issues an FPP invalidate line request. Alternatively, the source node could implement other forward progress techniques (e.g., retrying in the SSP mode or employing a token based protocol).
Each processor 54, 56, 58, and 60 also includes an associated cache 64, 66, 68 and 70. The caches 64, 66, 68, and 70 can enable faster access to data than from an associated main memory 72 of the processor 52. The system 50 implements a cache coherency protocol designed to guarantee coherency of data in the system. By way of example, the cache coherency protocol can be implemented to include a source broadcast protocol in which broadcast snoops or requests for data are transmitted directly from a source processor to all other processors and memory in the system 50. The source broadcast protocol can further be implemented in conjunction with another forward progress protocol, such as a null-directory or other directory-based protocol. The system 50 of
The memory 72 can include multiple memory modules (M1, M2, M3, M4) 74, 76, 78 and 80. For example, the memory 72 can be organized as a single address space that is shared by the processors 54, 56, 58 and 60 as well as other nodes 82 of the system 50. Each of the memory modules 74, 76, 78 and 80 can include a corresponding directory 84, 86, 88 and 90 that defines where the corresponding coherent copy of the data should reside in the system 50. Alternatively, the memory modules may contain no directories. A coherent copy of data, for example, may reside in a home node (e.g., associated with a given memory module) or, alternatively, in a cache of one of the processors 54, 56, 58 and 60.
The other node(s) 82 can include one or more other SMP nodes associated with the SMP processor 52 via the interconnect 62. For example, the interconnect 62 can be implemented as a switch fabric or hierarchical switch programmed and/or configured to manage transferring requests and responses between the processors 54, 56, 58, and 60 and the memory 70, as well as those to and from the other nodes 82.
When the processor 54 requires desired data, the processor 54 operates as a source and issues a source broadcast snoop (e.g., a broadcast read or broadcast write request) to the system 50, including all other processors 56, 58 and 60 as well as to memory 72, via the interconnect 62. The cache coherency protocol described herein is designed to ensure that a correct copy of the data is returned in response to the source broadcast snoop.
By way of example, assume that the processor 54 (a source processor) requires a copy of data associated with a particular memory address, and assume that the data is unavailable from its own local cache 64. Since the processor 54 does not contain a copy of the requested data, the cache line of the processor may be initially in the I-state (invalid) for that data or it may contain different data altogether. For purposes of simplicity of explanation, the starting state of the source processor cache line for this and other examples is the I-state. The processor 54, operating as the source processor, transmits a source broadcast read snoop (XREAD) to the other processors 56, 58, and 60, to the memory 72, and to the other nodes 82 via the interconnect 62.
In this example, it is assumed that, at the time of the XREAD request, at least one other processor (e.g., processor 56) in the system 50 has an outstanding XREAD request for the same data. It is further assumed that yet another processor (e.g., processor 58) is an owner processor, i.e., a cache ordering point for the data. For this example, assume that the owner processor 58 has a copy of the data in an M-state cache line of the owner processor.
For purposes of this example, assume that the cache ordering point is in the process of migrating from the owner processor 58 to the processor 56 at the time the processor 56 receives the XREAD request from the processor 54 (e.g., in response to the processor 56 receiving migratory data). The owner processor 58 transitions to the T-state after providing the D-DATA response to the processor 56. In this scenario, the processor 56 provides a CONFLICT message in response to the XREAD request of the processor 54 since the data state machine at the target processor is in the D-DATA state (see, e.g., Table 5). Also, the owner processor 58 provides a CONFLICT response to the processor 54 since the XREAD request from the processor 54 finds the owner processor 58 in the T-state. The memory 72 provides an M-DATA response to the XREAD request of the processor 54. Processor 60 provides a MISS response to the XREAD request of processor 54 because processor 60 is invalid for the cache line. As a result, after all responses to the XREAD request of the processor 54 have been received from the processors of the system 50, the data state machine associated with the XREAD request of the processor 54 is in the M-DATA state. Referring to the conflict state diagram of
Referring to Table 7, since the data state machine is in the M-DATA state and the conflict state machine is in the CONFLICT state, the resulting action taken at the processor 54 is to transition to the FPP mode and reissue an FPP request for the data. Thus, in this example, according to the cache coherency protocol described herein, the CONFLICT cannot be overcome and the system 50 reverts to the FPP mode to resolve the transaction with the processor 54. In doing so, the cache coherency protocol avoids filling incorrect or stale data at the processor 54.
The above example illustrates a conflict scenario that leads to one of the data state/conflict state combinations of Table 7. It will be appreciated that the other data state/conflict state combinations of Table 7 would similarly result in the corresponding source processor actions illustrated in Table 7. It will also be appreciated that the various data state and conflict state combinations of Table 7 may arise in a great number of circumstances involving conflict and non-conflict scenarios. The action taken at the source processor will be determined according to the data state/conflict state combination after all responses have been received at the source processor.
The system 100 can employ a source broadcast or source-snoopy cache coherency protocol. For this type of protocol, a source processor 102, 104, and 106 can issue a source broadcast request to all other processors in the system and to the memory 110. In the event that conflict arises, or the source broadcast request otherwise fails, the system 100 can transfer to a forward-progress protocol, such as a null-directory or other directory-based protocol.
In a null-directory-based protocol, for example, the memory 110 includes home nodes for each cache line. Instead of issuing a broadcast to all cache targets, the source issues a single request to the home node for such data. The home node thus operates as static ordering point for requested data since all requests are sent to the home node for ordering before snoops are broadcast. This tends to add an additional hop for the majority of references compared with a broadcast-based protocol described above. If the system employs a standard directory-based protocol, ordering is implemented, but the memory 110 employs associated directories that facilitate locating the data (e.g., based on the directory state associated with the requested data). In a standard directory protocol, there will be times when the directory can indicate that there are no cached copies, and thus the home node can respond with the data without issuing any snoops to the system 100.
The processor 102 includes cache memory 114 that contains a plurality of cache lines 116 (e.g., lines 1-M, where M is a positive integer, M≧1). Each cache line 116 can contain one or more memory blocks. A tag address (ADDRESS) is associated with the data contained in each cache line 116. Additionally, each cache line 116 can contain state information identifying the state of the data contained at that cache line. Examples of states that can be associated with each cache line 116 are identified above in Table 1.
A cache controller 118 is associated with the cache memory 114. The cache controller 118 controls and manages access to the cache memory, including requests for data and responses. The cache controller 118 communicates requests and responses via a switch interface 120 that is coupled with the switch fabric 108. The switch interface 120, for example, includes an arrangement of queues (e.g., input and output queues) or other data structures that organize both requests and responses issued by the processor 102 as well as requests and responses for execution by the processor.
In the example of
The cache controller 118 also includes a request engine 124 that sends requests to the system 100. The request engine 124 employs a miss address file (MAF) 126 that contains MAF entries for outstanding requests associated with some subset of the locations in the cache memory 114. The MAF can be implemented as a table, an array, a linked list or other data structure programmed to manage and track requests for each cache line. For example, when the processor 102 requires data associated with a given address for a given line 116, the request engine 124 creates a corresponding entry in the MAF 126. The MAF entry includes fields that identify, for example, the address of the data being requested, the type of request, and response information received from other nodes in response to the request. The request engine 124 thus employs the MAF 126 to manage requests issued by the processor 102 as well as responses to such requests. The request engine can employ a data state machine and conflict state machine (see, e.g.,
The cache controller 118 also includes a response engine 128 that controls responses provided by the processor 102. The processor 102 provides responses to requests or snoops received via the switch interface 120 from another processor 104 and 106 or memory 110. The response engine 128, upon receiving a request from the system 100, cooperates with the state engine 122 and the MAF 126 to provide a corresponding response based on the type of request and the state of data contained in the cache memory 114. For example, if a MAF entry exists for a tag address identified in a request received from another processor or memory, the cache controller can implement appropriate conflict resolution defined by the coherency protocol. The response engine thus enables the cache controller to send an appropriate response to requesters in the system 100. A response to a request can also cause the state engine 122 to effect a state transition for an associated cache line 116.
By way of example, assume that the processor 102 requires data not contained locally in its cache memory 114. The request engine 124 will create a MAF entry in the MAF 126, corresponding to the type of request and the tag address associated with data required. For a read request, for example, the processor 102 issues an XREAD request and allocates a corresponding entry in the MAF 126. For this example, assume that the processor 104 is an owner node including the data in a D-state cache line and assume that the processor 106 has an outstanding XRDINVAL MAF for the same data that has not yet been received at the owner processor 104. The cache controller 118 broadcasts a source snoop XREAD request to the nodes of the system 100 via the switch interface 120 and switch fabric 108.
In response to receiving the XREAD request from the source node 102, the memory 110 provides an M-DATA response. The owner node 104 provides a D-DATA response and transitions to the T-state (see, e.g., Table 4). The processor 106, having an outstanding XRDINVAL MAF for the data, responds to the XREAD by providing a non-data CONFLICT response (see, e.g., Table 5). After all responses have been received from the nodes of the system 100, the data state machine of the MAF 126 is in the D-DATA state and the conflict state machine of the MAF 126 is in the CONFLICT state. The resulting action taken at the source processor 102 is determined in accordance with Table 7.
Referring to Table 7, since the data state machine of MAF 126 is in the D-DATA state and the conflict state machine of MAP 126 is in the CONFLICT state, the resulting action taken at source processor 102 is to fill a cache line 116 of cache 114 with the D-DATA and employ the state engine 122 to transition the source processor cache line 116 associated with the data to the D-state. The source processor 102 then transitions to the migratory mode and employs the request engine 124 to broadcast an XINVAL command to all other processors. While the XINVAL is pending, the source processor 102 employs the response engine 128 to respond to any third party snoops with a CONFLICT message (see, e.g., Table 5). When all XINVAL acknowledgement responses have been received, the source processor 102 initiates an MACK/MACK-ACK sequence with the target processor 104 to complete the ordering point migration. Thus, in this conflicting read/write scenario involving migratory data, according to the cache coherency protocol described herein, the data migrates from the owner processor 104 to the source processor 102 and takes steps to correct any incorrect or stale data that may have been filled at other processors in the system 100.
The various examples of conflict scenarios depicted herein so far have been addressed from the perspective of only one of the conflicting processors in a given conflict scenario and considering the conditions at the other node to be essentially mostly static. These examples have not addressed the fact that in a conflict scenario, the source node and target node designations are relative. To illustrate this point, consider two processors, A and B, each of which have outstanding requests for the same data and therefore conflict with each other. From the point of view of processor A, processor A is the source node and processor B is the target node. From the point of view of processor B, processor B is the source node and processor A is the target node. It will thus be appreciated that in conflict scenarios, conflicting requests are handled by the cache coherency protocol at both conflicting nodes in the manner described herein. It will also be appreciated that the manner in which the requests of the conflicting processors are handled can depend in large part on the timing of the creation and/or retirement of the respective MAF entries at the conflicting processors and the timing of the respective snoops/responses of the conflicting processors.
In view of the foregoing structural and functional features described above, certain methods that can be implemented using a coherency protocol will be better appreciated with reference to
Referring to
The data state machine (see, e.g.,
As shown in
Referring to
In this conflicting read scenario involving migratory data, according to the cache coherency protocol described herein, the cache ordering point migrates from node 186 to node 182 in response to the XREAD request. Any incorrect or stale data that may have been filled at other nodes in the system 180 is cleaned-up via the XINVAL command issued by node 182 in the migratory mode. The RD-CONF conflict state machine indicates to node 182 that this clean-up of misleading RD-CONF states at other nodes may be necessary.
Referring to
After node 202 has transitioned to the D-state, node 204 receives an M-DATA response to an XREAD request broadcast from node 204 to home node 208. Node 204 then receives a MISS response to an XREAD request broadcast from node 204 to node 206 because the XREAD request finds node 206 in the I-state. At this point, responses have been received from all of the nodes to which node 204 broadcast snoop requests. Referring to
The data state machine (see, e.g.,
After node 222 issues the XINVAL command and receives the MISS response from node 224, node 224 allocates a RDMAF 232 and receives a CONFLICT response to an XREAD request broadcast from node 224 to node 222 because the RDMAF 232 is an XREAD and the data state machine is in the D-DATA state (see, e.g., Table 5). Next, node 224 receives an M-DATA response to an XREAD request broadcast from node 224 to home node 228. Next, node 224 receives a MISS response to an XREAD request broadcast from node 224 to node 226 because node 224 is in the I-state (see, e.g., Table 4).
At this point, responses have been received from all of the nodes to which node 224 broadcast the XREAD snoop request. Referring to
The data state machine (see, e.g.,
As shown in
Referring to
Thus, in the read/write conflict scenario involving migratory data in the example of
What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.
This application is related to the following commonly assigned co-pending patent applications: “CACHE COHERENCY PROTOCOL WITH ORDERING POINTS,” Attorney Docket No. 200313588-1; “SYSTEM AND METHOD FOR RESOLVING TRANSACTIONS IN A CACHE COHERENCY PROTOCOL,” Attorney Docket No. 200313589-1; “SYSTEM AND METHOD TO FACILITATE ORDERING POINT MIGRATION,” Attorney Docket No. 200313612-1; “SYSTEM AND METHOD TO FACILITATE ORDERING POINT MIGRATION TO MEMORY,” Attorney Docket No. 200313613-1; “SYSTEM AND METHOD FOR CREATING ORDERING POINTS,” Attorney Docket No. 200313614-1; “SYSTEM AND METHOD FOR CONFLICT RESPONSES IN A CACHE COHERENCY PROTOCOL WITH ORDERING POINT MIGRATION,” Attorney Docket No. 200313615-1; “SYSTEM AND METHOD FOR READ MIGRATORY OPTIMIZATION IN A CACHE COHERENCY PROTOCOL,” Attorney Docket No. 200313616-1; “SYSTEM AND METHOD FOR BLOCKING DATA RESPONSES,” Attorney Docket No. 200313628-1; “SYSTEM AND METHOD FOR NON-MIGRATORY REQUESTS IN A CACHE COHERENCY PROTOCOL,” Attorney Docket No. 200313629-1; “SYSTEM AND METHOD FOR CONFLICT RESPONSES IN A CACHE COHERENCY PROTOCOL,” Attorney Docket No. 200313631-1; “SYSTEM AND METHOD FOR RESPONSES BETWEEN DIFFERENT CACHE COHERENCY PROTOCOLS,” Attorney Docket No. 200313632-1, all of which are filed contemporaneously herewith and are incorporated herein by reference.
