FIELD OF INVENTION
The present invention relates to back drilling in printed circuit boards (PCBs). In particular the present invention relates to detecting poor or failed back-drills in printed circuit boards.
A failed back-drill in a PCB is one that does not remove all of the metal in the drilled hole or via. This can be due to any of a variety of reasons during the PCB fabrication process such as a drill-misalignment. FIG. 1 Illustrates drill misalignment. A failed drill-back will leave a conductive path of some or all of the length of the drilled via. The via stub created by the failed drill-back results in a degradation of high frequency signals in that path in the PCB.
THE RELATED PRIOR ART
Common PCB testing is accomplished by measuring opens and shorts by employing a flying-probe test. However, these testers are not able to detect a failed back-drill. It is necessary to utilize high-speed test tools such as a Vector Network Analyzer or a Time domain Reflectometer in order to see the failed back-drill but these tools are expensive, difficult to implement in scale and produce difficult to analyze results. Visual inspection has a limited 1820Application for Method for Detecting Failed or Poor Back Drills in Printed Circuit Boards success rate of detecting back-drill problems and 3D X-rays machines are both expensive and unreliable.
SUMMARY OF THE INVENTION
It would therefore be advantageous to have a novel method for detecting failed or poor back-drills in PCBs that avoids the drawbacks of the aforementioned prior art proposals.
Embodiments in accordance with the present invention provides a method for detecting failed back-drills in PCBs early in the process of fabricating a PCB so that the failed back-drill can be screened out or repaired.
In accordance with an embodiment of the present invention, a short to ground connection is added near the signal layer for every back-drill. This short to ground connection is cut by a successful back-drill. If the back-drill is bad or failed it will leave the connection to ground and fail the electrical test with a short to ground being detected. The PCB can be repaired by re-drilling the hole or via.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Unless otherwise noted, the drawings may not be drawn to scale.
FIG. 1A shows the placement of the short to ground near a signal layer of the PC;
FIG. 1B shows a good back-drill in a PCB;
FIG. 1C shows a bad back-drill in a PCB;
FIG. 2A shows the selected, configured or design PCB with a transmission line consisting of a via, a signal trace, another a via, and two stubs before back-drilling;
FIG. 2B shows shorting the signal trace to ground in a hole or a via of the PCB;
FIG. 2C shows a bad back-drill failure due to drill shift;
FIG. 2D shows a bad back-drill failure due to drill wander;
FIG. 2E shows a bad back-drill failure due to shallow drill;
FIG. 2F shows one example of electrical connection to ground failure;
FIG. 2G shows another example of electrical connection to ground failure;
FIG. 2H shows another example of electrical connection to ground failure;
FIG. 2I illustrates a back-drill cutting an electrical connection to a power plane;
FIG. 2J shows two back-drills that removed a two via stubs;
FIG. 3 illustrates the methodology of the present invention; FIG. 3 shows one method of how the invention can be automated in the PCB design process and integrated with manufacturing the PCB for opens and shorts to determine if, among other things, all of the back-drills removed all of the short to ground connections.
FIG. 4 illustrates a plan view of a portion of an exemplary layer of a printed circuit board, in accordance with embodiments of the present invention.
DETAILED DESCRIPTION
Reference will now be made in detail to various embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it is understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be recognized by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.
Some portions of the detailed descriptions which follow (e.g., the method of FIG. 3) are presented in terms of procedures, steps, logic blocks, processing, and other symbolic representations of operations on data bits that may be performed on computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, computer executed step, logic block, process, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, data, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as “testing” or “heating” or “maintaining temperature” or “bringing” or “capturing” or “storing” or “reading” or “analyzing” or “generating” or “resolving” or “accepting” or “selecting” or “determining” or “displaying” or “presenting” or “computing” or “sending” or “receiving” or “reducing” or “detecting” or “setting” or “accessing” or “placing” or “testing” or “forming” or “mounting” or “removing” or “ceasing” or “stopping” or “coating” or “processing” or “performing” or “generating” or “adjusting” or “creating” or “executing” or “continuing” or “indexing” or “translating” or “calculating” or “measuring” or “gathering” or “running” or the like, refer to the action and processes of, or under the control of, a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
The meaning of “non-transitory computer-readable medium” should be construed to exclude only those types of transitory computer-readable media which were found to fall outside the scope of patentable subject matter under 35 U.S.C. § 101 in In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007). The use of this term is to be understood to remove only propagating transitory signals per se from the claim scope and does not relinquish rights to all standard computer-readable media that are not only propagating transitory signals per se.
SYSTEM AND METHOD FOR DETECTING DEFECTIVE BACK-DRILLS IN PRINTED CIRCUIT BOARDS
The referenced elements for the present invention include:
- 1. PCB 5.
- 2. Via or hole 8.
- 3. Shorting trace 10.
- 4. Signal level or trace or stripline 16.
- 5. Back-drill 15.
- 6. Ground or power plane 23.
7. Transmission line or signal path 11.
As is known in the art, a printed circuit board, e.g., PCB 5, typically comprises a plurality of layers, e.g., ground or power layers 23 and signal level layers 16. These exemplary layers are illustrated in cross sectional views in FIGS. 1A, 1B, 1C, 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 21, and 2J. An exemplary signal layer 16 is illustrated in plan view in FIG. 4. A plurality of vias 8 provide electrical coupling for traces formed on different layers of the PCB. For example, as illustrated in FIG. 2A, a first instance of via 8 couples a portion of signal path 11 on a first layer of the PCB to a second layer of the PCB, while a second instance of via 8 couple couples another portion of signal path 11 from the second layer of the PCB to a third layer of the PCB.
A printed circuit board (PCB) has two opposing external major surfaces, one or both of which may bear circuitry, including, for example, conductive traces or patterns. In addition, multilayer PCBs are well known in which one or more layers of conductive traces or patterns are disposed in between the two opposing external major surfaces. Vias are commonly used to connect signals on any one of these layers to any other one of these layers. A via is generally a hole that is drilled or otherwise formed in the PCB and plated or filled with copper or another conductor. Vias may pass through the entire PCB, or have a limited extent, e.g., a via may pass through some but not all layers of a PCB. Vias generally electrically couple traces on two or more layers of a PCB, and are generally electrically isolated from some layers of the PCB.
FIG. 1A illustrates an exemplary cross sectional view of a portion of a multi-layer printed circuit board (PCB) 5, in accordance with embodiments of the present invention. PCB 5 comprises a plurality of layers, including multiple power or ground plane layers 23, and at least one signal layer, e.g., a layer primarily for conducting signals that are not ground or power. Such layers may be known as or referred to as non-ground and/or non-power layers. Signal trace 16 is on a signal layer. Via 8 is a portion of signal path 11 (FIG. 2A). Via 8 conducts a portion of signal path 11 from one signal layer, e.g., a layer comprising signal trace 16, to a portion of signal path 11 located on a different signal layer, for example, on a top surface of PCB 5. Referring now to the drawings, FIG. 1A, in accordance with the teachings of the present invention illustrates the methodology of the present invention wherein in the PCB design a short to ground connection 10 (hereinafter referred to as a shorting trace 10) is added into the design a programmed distance from the signal trace 16 that electrically connects or shorts the signal via 8 to ground. Thus there is a placement of the shorting trace 10 near a signal trace 16 of the PCB 5. Therefore if, for example, a 10 mil±5 mils back-drill 15 is drilled in a hole or via 8 of the PCB 5, the shorting trace 10 is placed on the first ground layer 16 mils past the signal trace or strip line 16. When a successful back-drill operation is performed the back-drill 15 breaks the electrical connection between signal trace 16 and ground. If the back-drill 15 fails it will leave a path of conductive material in the signal via 8 that will still short signal trace 16 to ground 10 at that sign at that signal trace 16. A failed back-drill is illustrated in FIGS. 2H, 2G and 2I. A good back-drill is shown FIG. 1BFIG. 2J.
FIG. 4 illustrates a plan view of a portion of an exemplary layer of a printed circuit board (PDB) 5, in accordance with embodiments of the present invention. The layer comprises a number of conductive traces or patterns. Signal trace 16 is a portion of signal path 11 (FIG. 2A). As previously presented, e.g., with respect to FIG. 2A, signal path 11 comprises traces, e.g., signal trace 16 on the illustrated layer, and other signal trace(s) on other layer(s) of PCB 5. Via 8 (non-ground via) couples signal trace 16 of signal path 11 with one or more other signal traces of signal path 11 on other layer(s) of the PCB. Via 8 may also be used for testing, e.g., as a test point or test via, in some embodiments.
FIG. 2A shows a PCB with transmission line path 11 from top left to bottom right. The transmission line comprises a via 8, a trace or stripline 16, and a via 8. Via stubs 10 are also present. The via 8 is nominally not coupled to ground, e.g., the line path 11, comprising via 8, is not schematically coupled to ground. The via 8 may be known as or referred to as a non-ground via. Similarly, via 8 is nominally not coupled to power, and may be known as or referred to as a non-power via.
FIG. 2B shows a shorting trace 6 connecting the via 11.
FIGS. 2C-2E show common back-drill failure modes.
FIG. 2C shows a back-drill failure due to drill shift. FIG. 2 E shows a bad back-drill failure due to drill wander. Drill wander is when a drill does not drill straight down into the PCB 5 but instead curves away from a straight up or down path FIG. 2F shows a back-drill failure due to shallow drill. A shallow drill is one that leaves a stub 10 longer than the maximum stub length allowed.
FIGS. 2F-2H show common back-drill failure modes with a shorting trace 6 connecting signal to ground.
FIG. 2I shows a back-drill 15 that cuts the shorting trace signal to ground or power plane 23 connection.
FIG. 2J shows a PCB 5 with back-drill 15 that removed the via stubs 8.
FIG. 3 illustrates the methodology of the present invention. In FIG. 3 illustrates a first step of the methodology of the present invention in which a design or configured PCB 5 is selected. Next FIG. 3 shows a second step 18 in which shorting traces 10 are added to back-drilled vias 8 in the PCB 5 design.
FIG. 3 illustrates a third step of the methodology in which the PCB 5 is designed 17 and subsequently the electronic design files are modified using automated software 18 to add shorting traces for each back-drilled via. The PCB 5 is then manufactured 19 using common PCB manufacturing techniques. It is then tested 20 to verify each transmission line 11 is electrically isolated from ground 23 to confirm the back-drill 15 cut the shorting trace confirming a good back-drill. Such testing may be performed by a well-known “flying-probe test.” For example, a flying probe test places a first probe on a first via, e.g., via 8, and a second probe on a second via, and tests for continuity between the first and second vias. A via used in this manner for testing may be know as, or referred to as a test signal via or test point. In general, any via may be used for testing, and any signal path may be used as a test signal. As is known, there may be dedicated test signals and/or signal paths, e.g., a signal path used only for testing. If there is a short, e.g., transmission line 11 is coupled to ground, then the back-drill 15 has failed and the PCB 5 must be discarded or repaired.
The methodology of the claimed invention is preferably software implemented in the following steps:
- 1. Execute the program and select the design files
- 2. There are three sections
- Back Drill
- Compare IPC
- Compare Shorts.
- 3. The first section “Back Drill” will update all hack drill vias to create intentional short to ground.
- 4. The second section “Compare IPC” will compare the board files before and after intentional short to verify correct functionality
- 5. The third section “Compare Shorts” compares the error checking output files to the expected errors that are generated from this software. The shorting of a signal via to ground will create a DRC error that other computer aided manufacturing software will detect. CAM 350 is an example of Gerber Computer Aided Manufacturing tool that will detect said errors. This section will make sure that other unrelated errors are separated from errors caused by this process
- B. Back-Drill program details
- 1. User implements the following parameters:
- a. Via stub length: This value is the minimum stub length before a short can be added (E.g. 10 mils)
- b. Ground net: This is the name of the ground net in the PCB design software. (E.g. “VSS”)
- c. Copper Web: This value is the copper web in the custom antipad allowing ground copper to flow in the back drill vias by default the tool will use a value of 5 mils.
- d. Copper Diameter: This is the copper diameter around the hole.
- Program steps include:
- 2. Execute program:
- a. Load PCB design file.
- b. Loop through all back drilled via locations
- c. Start at trace depth, define this as position 0
- d. Subtract “via stub length” from this position 0 (E.G. 0−10=−10)
- e. Start at this calculated position and look for closest “Ground net” copper plane while moving away from the trace location. (E.G. “VSS layer located at −16.5 mils”)
- f. Add shorting feature defined by “Ground Web” and “Copper Diameter” (E.G. see picture)
- g. Rename design file via name to customer name indicating anti-pad modification.
- h. Create report file indicating changes made
The methodology of the present invention is assisted from tools improvements in a typical PCB design flow. All common PCB design tools have a design rule check, also known as DRC that looks for nets that are shorted together as well as other error checking. A program or script adds the shorting trace 10 at all back-drill 15 locations and adjusts the depth of the shorting trace 10 by the tolerance of the back-drill 15 and the depth of the signal trace 6.
Once the shorting traces 10 are added the common PCB design or Gerber files then computer added manufacturing, A.K.A. CAM, tools will show DRC errors. The back-drill shorting trace 10 DRC flags must be identified and screened out so DRC flags for legitimate errors are caught and fixed. It is understood that although copper web is preferably used any suitable electrically conductive metallic material can be used.
Various embodiments of the invention are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.
Patent Application
20250085332
