SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT

Abstract

A system and method for testing an integrated circuit is disclosed. One embodiment includes at least one central processing unit, at least one volatile memory area, and an interface is suggested, wherein the memory area is adapted to be written by the interface. The system includes a test device connected with the integrated circuit which is configured to stop the program execution, write data in the volatile memory by using the interface, and start the program execution.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIG. 1 illustrates a schematic representation of an inventive integrated circuit 1 in which functional groups are schematically illustrated as blocks.

Claims

1. A system for testing an integrated circuit comprising: at least one central processing unit;at least one volatile memory area;an interface, wherein the memory area is configured to be written using the interface; anda test device coupled with the integrated circuit, wherein the test device is configured to stop program execution, write data in the volatile memory area via the interface, and start program execution.

2. The system of claim 1, wherein the integrated circuit comprises: a circuit for stopping and starting the program execution including a register configured to be written via the interface.

3. The system of claim 2, comprising wherein a signal line of the circuit for stopping and starting the program execution is guided to a connecting contact of the circuit.

4. The system of claim 1, comprising a non-volatile memory area.

5. The system of claim 1, wherein the integrated circuit comprises an address decoder for assigning physical memory addresses to logic addresses.

6. The system of claim 5, comprising wherein the address decoder is configurable via the interface.

7. The system of claim 5, comprising wherein at least a partial area of the volatile memory is configurable as an overlay RAM by the address decoder.

8. The system of claim 1, wherein the interface comprises a serial bus interface of any protocol.

9. The system of claim 1, wherein the interface comprises a test interface pursuant to the JTAG Standard IEEE 1149.

10. The system of claim 1, wherein the interface comprises a Universal Serial Bus interface.

11. The system of claim 1, comprising wherein the memory area is readable by the interface.

12. A method for testing an integrated circuit comprising: defining the integrated to include at least one central processing unit, a volatile memory area connected therewith, and an interface connected with the memory area;stopping a program execution;writing data in the volatile memory via the interface; andstarting the program execution.

13. The method according to claim 12, comprising stopping the program execution during the switch-on starting procedure.

14. The method of claim 12, comprising stopping a clock signal of the central processing unit for stopping the program execution.

15. The method of claim 12, comprising wherein the central processing unit, for stopping the program execution, examines the content of a register and, depending on the content, runs in a waiting loop.

16. The method of claim 12, comprising wherein, prior to the starting of the execution of the program, the physical address of the volatile memory is, in an address decoder, configured as address of the data to be processed.

17. The method of claim 12, comprising stopping the program execution as soon as the volatile memory area and the address decoder are ready to be written.

18. The method of claim 12, comprising wherein the central processing unit examines the content of a register at least during the switch-on starting procedure, and the program execution is stopped depending on the content of the register.

19. The method of claim 12, comprising writing only parameter values in the volatile memory.

20. The method of claim 12, comprising writing a terminated program with the parameter data to be processed in the volatile memory.

21. The method of claim 12, wherein, after the starting of the program execution, the same is stopped and the volatile memory is read by the interface.

22. The method of claim 12, wherein, prior to the stopping of the program execution, it is tested by means of a test device connected with the integrated circuit whether the integrated circuit is ready for operation.

23. A system for testing an integrated circuit comprising: at least one central processing unit;at least one volatile memory area;an interface, wherein the memory area is configured to be written using the interface;a test device coupled with the integrated circuit, wherein the test device is configured to stop program execution, write data in the volatile memory area via the interface, and start program execution; andmeans for stopping and starting the program execution including a register configured to be written via the interface.