Claims
- 1. A system comprising:A. a microprocessor device having data pins carrying data signals, address pins carrying address signals, and control outputs carrying control signals, the microprocessor device being capable of receiving data signals at the data pins a certain period of time after sending address and control signals and being capable of performing a desired number of wait states after sending address and control signals, the microprocessor device including at least two wait state registers, each wait state register containing a number defining a number of wait states, each wait state register being connected to the data signals to receive data signals representing a number defining a number of wait states, and each wait state register being coupled to the address signals; B. at least two external devices external of the microprocessor device, each external device having data pins, address pins and a control input connected to the control outputs of the microprocessor device, each external device producing data at the data pins after receiving address signals in a separate segment of the external memory space; C. an external data bus connecting together the respective data pins of the microprocessor device and the external devices; and D. an external address bus connecting together the respective address pins of the microprocessor device and the external devices.
- 2. The system of claim 1 in which one of the external devices is a memory device.
- 3. The system of claim 1 in which one of the external devices is a peripheral device.
- 4. The system of claim 1 in which the wait state registers each contain a binary number of from zero to fifteen.
- 5. The system of claim 1 in which the wait state registers each contain a number having at least four binary bits.
- 6. The system of claim 1 in which one of the external device provides data to the microprocessor device slower than the certain period of time.
- 7. The system of claim 1 in which one of the external device provides data to the microprocessor device slower than the certain period of time and each external device provides data to the microprocessor in a period of time different from the other external device.
CROSS REFERENCE TO RELATED APPLICATIONS
This patent is related to co-assigned U.S. Pat. Nos. 5,586,275; 5,072,418; 5,142,677; 5155,812; 5,829,054; and 5,724,248, all filed contemporaneously herewith and incorporated herein by reference.
This application is a divisional of application Ser. No. 09/360,488, filed Jul. 23, 1999, now pending; which is a divisional of application Ser. No. 08/906,863, filed Aug. 6, 1997, now U.S. Pat. No. 5,946,483; which is a divisional of application Ser. No. 08/293,259, filed Aug. 19, 1994, now U.S. Pat. No. 5,907,714; which is a continuation of application Ser. No. 07/967,942, filed Oct. 28, 1992, now abandoned; which is a continuation of application Ser. No. 07/347,967, filed May 4, 1989, now abandoned.
This invention relates to data processing devices, electronic processing and control systems and methods of their manufacture and operation.
US Referenced Citations (26)
Non-Patent Literature Citations (5)
Entry |
Second Generation TMS320 User's Guide; pp. 3-6.* |
“DSP56000 Digital Signal Processor's User's Manual”, Motorola, 1986, pp. 2-12-18, 3-2, 7-1-3. |
“DSP96001”, Motorola, 1998, pp. 1, 2, 6, 9, 10. |
Second-Generation TMS320 User's Guide, Texas Instruments, pp. 6-10-26,Dec. 1987. |
First-Generation TMS320 User's Guide, Texas Instruments, pp. 3-9, A-1-20, 6-2-5, Apr. 1988. |
Continuations (2)
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Number |
Date |
Country |
Parent |
07/967942 |
Oct 1992 |
US |
Child |
08/293259 |
|
US |
Parent |
07/347967 |
May 1989 |
US |
Child |
07/967942 |
|
US |