Patent Application
20250126724
The present disclosure relates in general to information handling systems, and more particularly to forming nonfunctional pads on a conductive layer of a circuit board during manufacturing to act as a filler in a conductive layer of the circuit board in order to minimize an amount of resin of an insulative layer that fills the conductive layer during manufacturing.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems may often use one or more circuit boards. A circuit board may comprise a substrate of a plurality of conductive layers separated and supported by layers of dielectric insulating material laminated together, with conductive traces disposed on and/or in any of such conductive layers, with vias for coupling conductive traces of different layers together, and with pads for coupling electronic components (e.g., packaged integrated circuits, slot connectors, etc.) to conductive traces of the circuit board.
Density of signal routing in circuit boards has been increasing with each new generation, motivating the use of thinner dielectric layers. Thinner dielectric layers may also minimize signal crosstalk.
Each conductive layer 402 may be made from a foil of conductive metal (e.g., copper). Nonfunctional pads, which may be provided to provide extra clearance between functional pads to prevent electrical shorting between functional pads of the same layer, may be formed during manufacturing and subsequently removed, resulting in a large antipad 406 or cavity that encourages prepreg flow and may result in cross-section geometry variations during lamination. To illustrate, when prepreg is used in areas adjacent to antipads 406 (e.g., regions in which vias may be formed), resin of an adjacent prepreg layer 404a, 404c, or 404e may fill regions of antipads 406. Such resin flow, shown by arrows in
In accordance with the teachings of the present disclosure, the disadvantages and problems associated with existing approaches to mounting a circuit package to a printed circuit board may be reduced or eliminated.
In accordance with embodiments of the present disclosure, a circuit board may include a plurality of electrically-conductive layers and a plurality of electrically-insulative layers laminated together with the plurality of electrically-conductive layers such that each of the plurality of electrically-insulative layers is located between adjacent layers of the plurality of electrically-conductive layers. A first electrically-conductive layer of the plurality of electrically-conductive layers may be patterned, during a process step in the manufacture of the circuit board, to include an electrically-conductive pattern patterned to be electrically coupled to an electrically-conductive network within the circuit board and a nonfunctional pad comprising a portion of conductive material patterned from the first electrically-conductive layer but electrically decoupled from the electrically-conductive pattern. A first electrically-insulative layer of the plurality of electrically-insulative layers may be laminated over the first electrically-conductive layer such that resin of the first electrically-insulative layer fills a void between the electrically-conductive network and the nonfunctional pad.
In accordance with these and other embodiments of the present disclosure, a method for forming a circuit board may include laminating a plurality of electrically-conductive layers and a plurality of electrically-insulative layers such that each of the plurality of electrically-insulative layers is located between adjacent layers of the plurality of electrically-conductive layers and patterning, during a process step in the manufacture of the circuit board, a first electrically-conductive layer of the plurality of electrically-conductive layers to include an electrically-conductive pattern patterned to be electrically coupled to an electrically-conductive network within the circuit board a nonfunctional pad comprising a portion of conductive material patterned from the first electrically-conductive layer but electrically decoupled from the electrically-conductive pattern. The method may also include laminating, during another process step in the process step in the manufacture of the circuit board, a first electrically-insulative layer of the plurality of electrically-insulative layers over the first electrically-conductive layer such that resin of the first electrically-insulative layer fills a void between the electrically-conductive network and the nonfunctional pad.
Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure.
A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:
Preferred embodiments and their advantages are best understood by reference to
For the purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system may be a personal computer, a personal digital assistant (PDA), a consumer electronic device, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include memory, one or more processing resources such as a central processing unit (“CPU”), microcontroller, or hardware or software control logic. Additional components of the information handling system may include one more or devices, storage one or more communications ports for communicating with external devices as well as various input/output (“I/O”) devices, such as a keyboard, a mouse, and a video display. The information handling system may also include one or more buses operable to transmit communication between the various hardware components.
For the purposes of this disclosure, computer-readable media may include any instrumentality or aggregation of instrumentalities that may retain data and/or instructions for a period of time. Computer-readable media may include, without limitation, storage media such as a direct access storage device (e.g., a hard disk drive or floppy disk), a sequential access storage device (e.g., a tape disk drive), compact disk, CD-ROM, DVD, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and/or flash memory; as well as communications media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and/or optical carriers; and/or any combination of the foregoing.
For the purposes of this disclosure, information handling resources may broadly refer to any component system, device or apparatus of an information handling system, including without limitation processors, service processors, basic input/output systems (BIOSs), buses, memories, I/O devices and/or interfaces, storage resources, network interfaces, motherboards, and/or any other components and/or elements of an information handling system.
For the purposes of this disclosure, circuit boards may broadly refer to printed circuit boards (PCBs), printed wiring boards (PWBs), printed wiring assemblies (PWAs), etched wiring boards, and/or any other board or similar physical structure operable to mechanically support and electrically couple electronic components (e.g., packaged integrated circuits, slot connectors, etc.). A circuit board may comprise a substrate of a plurality of conductive layers separated and supported by layers of insulating material laminated together, with conductive traces disposed on and/or in any of such conductive layers, with vias for coupling conductive traces of different layers together, and with pads for coupling electronic components (e.g., packaged integrated circuits, slot connectors, etc.) to conductive traces of the circuit board.
As shown in
Chassis 100 may include any suitable housing or enclosure configured to house the various components of information handling system 102, and may be constructed from metal, plastic, and/or any other suitable material.
Motherboard 101 may comprise a circuit board configured to provide structural support for one or more information handling resources of information handling system 102 and/or electrically couple one or more of such information handling resources to each other and/or to other electric or electronic components external to information handling system 102.
Processor 103 may include any system, device, or apparatus configured to interpret and/or execute program instructions and/or process data, and may include, without limitation, a microprocessor, microcontroller, digital signal processor (DSP), application specific integrated circuit (ASIC), or any other digital or analog circuitry configured to interpret and/or execute program instructions and/or process data. In some embodiments, processor 103 may interpret and/or execute program instructions and/or process data stored in a storage resource, memory system 104, and/or another component of information handling system 102.
Memory 104 may be communicatively coupled to processor 103 and may comprise any system, device, or apparatus operable to retain program instructions or data for a period of time (e.g., computer-readable media). Memory 104 may comprise random access memory (RAM), electrically erasable programmable read-only memory (EEPROM), a PCMCIA card, flash memory, magnetic storage, opto-magnetic storage, or any suitable selection and/or array of volatile or non-volatile memory that retains data after power to information handling system 102 is turned off. In particular embodiments, memory 104 may comprise dynamic random access memory (DRAM).
Expansion card 106 may comprise any suitable circuit board. In some embodiments, expansion card 106 may comprise a riser card.
In addition to motherboard 101, processor 103, memory 104, and expansion card 106, information handling system 102 may include one or more other information handling resources.
As shown in
Each conductive layer 202 may be made from a foil of conductive metal (e.g., copper). As shown in
Rather than removing nonfunctional pads 208 during manufacture prior to adding adjacent prepreg layers, as is typically the case in traditional approaches, such nonfuctional pads may remain while adjacent prepreg layers are formed. When prepreg is used in areas adjacent to antipads 206 (e.g., regions in which vias may be formed), resin of an adjacent prepreg layer 204a, 204c, or 204e may fill regions of antipads 206, as shown by arrows in
For purposes of clarity and exposition, resin flow from prepreg layers 204a and 204e into antipads 206 is not shown in
As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements.
This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set.
Although exemplary embodiments are illustrated in the figures and described above, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the figures and described above.
Unless otherwise specifically noted, articles depicted in the figures are not necessarily drawn to scale.
All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.
Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description.
To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112 (f) unless the words “means for” or “step for” are explicitly used in the particular claim.
