Patent Application
20250196283
This disclosure relates to systems and methods for substrate processing, including methods for processing interposer substrates.
In the manufacture of semiconductor devices, densification of components, such as may be accomplished by reducing feature sizes can aid in producing high-performance, low-power devices. Heterogenous integration, such as multi-chip modules (MCM) or three-dimensional integrated circuits (3DIC) can make use of interposers to connect multiple semiconductive dies.
As devices incorporate increasing sizes and numbers of semiconductive dies, interposer complexity exhibits corresponding increases. For example, interposers can exhibit greater numbers of connections or increased density of those connections. However, some applications used for interposers may be optimized for relatively coarse routing. For example, a redistribution layer (RDL) can be implemented with an organic dielectric, such as polyimide or epoxy, and may be deposited according to additive patterning, eschewing a CMP/G operation. Such an approach can realize line and space dimensions of about two micrometers. By contrast, interconnects of the integrated circuits connected by the substrate can exhibit line and space dimensions of well under one micrometer (e.g., 400 nanometers).
Moreover, the size of the interposers themselves may increase. As the size of the interposers approaches a same order of magnitude of a wafer itself, a non-functional area of a wafer, such as an edge exclusion area (along with any scribe lines) can occupy an increasing proportion of the wafer. Such a proportion can hold true, even for relatively large wafers, such as 300-millimeter circular wafers. Accordingly, interposer substrates may be generated from rectangular panels to reduce or eliminate the dimensions of an edge exclusion area. However, these panels may complicate aspects of fabrication as may have evolved for applications including circular wafers. For example, applying a CMP/G process to a rectangular panel can lead to asymmetries (e.g., excessive polishing/grinding of the corners).
Systems and methods of the present disclosure can generate interposers exhibiting line and space dimensions of less than one micrometer, without applying a CMP/G process as may lead to substantial asymmetries. For example, a chemical polishing process can uniformly etch an upper surface of a substrate (e.g., a copper, silicon, or organic layers). The chemical polishing process can be performed as between a chemically active substance as may be provided in solution (e.g., in a chemical pad in contact with the rectangular panel). Although some force may be applied to the pad to maintain contact with the rectangular panel, such a force is not provided to facilitate a mechanical grinding or polishing operations. Further, an abrasive pad, slurry, or electric current applied to the substrate may be omitted, such that all or substantially all of the planarization process is achieved via the chemical polishing process.
Of course, the order of discussion of the different steps as described herein has been presented for clarity's sake. In general, these steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of this disclosure, it is intended that each of the concepts can be executed independently of each other or in combination with each other. Accordingly, the present invention can be embodied and viewed in many different ways.
In some aspects, the techniques described herein relate to a method, including: providing a polygonal panel with a conductive layer; and polishing an upper surface of the polygonal panel using a chemical polishing process.
In some aspects, the techniques described herein relate to a method, wherein the chemical polishing process uses an etching chemical and a passivating chemical.
In some aspects, the techniques described herein relate to a method, wherein the conductive layer includes copper and the etching chemical is selective to copper.
In some aspects, the techniques described herein relate to a method, wherein the etching chemical includes at least one of a peroxide or hydroxide.
In some aspects, the techniques described herein relate to a method, wherein the passivating chemical includes Benzotriazole (BTA).
In some aspects, the techniques described herein relate to a method, wherein the panel is a glass panel having a rectangular shape that is greater than 300 mm along at least one lateral dimension rectilinear to an edge of the rectangular shape.
In some aspects, the techniques described herein relate to a method, wherein the abrasive free chemical polishing process is conducted through a polishing pad, the pad having a surface area that is at least fifty percent smaller than the panel, the polishing pad free of materials that are abrasive to the conductive layer.
In some aspects, the techniques described herein relate to a method, wherein the polishing pad is rotated while the panel is maintained in a fixed position.
In some aspects, the techniques described herein relate to a method, wherein polishing pad is moved relative to a surface of the polygonal panel.
In some aspects, the techniques described herein relate to a method including: providing a polygonal panel with a layer to be polished; and polishing the layer on the polygonal panel using a chemical polishing process with a polishing pad providing a downforce pressure between the polishing pad and the polygonal panel of less than one psi.
In some aspects, the techniques described herein relate to a method, wherein the chemical polishing process includes providing a liquid including an etching chemical and a passivating chemical.
In some aspects, the techniques described herein relate to a method, wherein the etching chemical corrodes the layer.
In some aspects, the techniques described herein relate to a method, wherein the layer includes copper.
In some aspects, the techniques described herein relate to a method, wherein the etching chemical includes at least one of a peroxide or hydroxide.
In some aspects, the techniques described herein relate to a method, wherein the passivating chemical is Benzotriazole (BTA).
In some aspects, the techniques described herein relate to a method, wherein the panel is a glass panel rectangular shape that is greater than 300 mm along at least one lateral dimension rectilinear to an edge of the rectangular shape.
In some aspects, the techniques described herein relate to a method, wherein the downforce pressure is less than 0.5 psi.
In some aspects, the techniques described herein relate to a method, wherein the chemical polishing process includes providing a surfactant including at least one of sodium dodecyl sulphate (SDS) or cetyltrimethyl ammonium bromide (CTAB).
In some aspects, the techniques described herein relate to a method, wherein the glass panel is retained with a rectangular retention assembly during the chemical polishing process.
These and other aspects and implementations are discussed in detail below. The foregoing information and the following detailed description include illustrative examples of various aspects and implementations, and provide an overview or framework for understanding the nature and character of the claimed aspects and implementations. The drawings provide illustrations and a further understanding of the various aspects and implementations, and are incorporated in and constitute a part of this specification. Aspects can be combined, and it will be readily appreciated that features described in the context of one aspect of the invention can be combined with other aspects. Aspects can be implemented in any convenient form. As used in the specification and in the claims, the singular form of “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.
References to “or” may be construed as inclusive so that any terms described using “or” may indicate any of a single, more than one, and all of the described terms. References to at least one of a conjunctive list of terms may be construed as an inclusive OR to indicate any of a single, more than one, and all of the described terms. For example, a reference to “at least one of ‘A’ and ‘B’” can include only ‘A’, only ‘B’, as well as both ‘A’ and ‘B’. Such references used in conjunction with “comprising” or other open terminology can include additional items.
Non-limiting embodiments of the present disclosure are described by way of example with reference to the accompanying figures, which are schematic and are not intended to be drawn to scale. Unless indicated as representing the background art, the figures represent aspects of the disclosure. For purposes of clarity, not every component may be labeled in every drawing. In the drawings:
Reference will now be made to the illustrative embodiments depicted in the drawings, and specific language will be used here to describe the same. It will nevertheless be understood that no limitation of the scope of the claims or this disclosure is thereby intended. Alterations and further modifications of the inventive features illustrated herein, and additional applications of the principles of the subject matter illustrated herein, which would occur to one skilled in the relevant art and having possession of this disclosure, are to be considered within the scope of the subject matter disclosed herein. Other embodiments may be used and/or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to be limiting of the subject matter presented.
Techniques herein include methods and devices for polishing of polygonal panels. Specifically, techniques include low pressure chemical polishing processes which can planarize a surface of a polygonal panel. The low pressure can avoid cracking or fracturing of the panel as may occur in higher pressure systems (e.g., at panel corners or other edges). The polygonal panel can include, for example, various interposer substrate, such as glass substrates joined on a monolithic panel, prior to dicing. The method can include use of non-abrasive etchants to remove an upper surface of a layer formed over the substrate of the interposer. Such layers can include, for example, organic or other dielectrics, as well as conductive elements of a redistribution layer (RDL) structure. The use of the planarization techniques rather than additive processes alone can improve a minimum feature size of the RDL structure which can, in turn, improve signal routing, density, power efficiency, and other aspects of heterogeneously integrated devices. Moreover, the use of a slurry free chemical polishing process can reduce nanoparticle waste and reduce pad glazing.
Reference will now be made to the figures, which for the convenience of visualizing the fabrication techniques described herein, illustrate a variety of materials undergoing a process flow in various views. Unless expressly indicated otherwise, each Figure represents one (or a set) of fabrication steps in a process flow for manufacturing the devices described herein. In the various views of the Figures, connections between conductive layers or materials may or may not be shown. However, it should be understood that connections between various layers, masks, or materials may be implemented in any configuration to create electric or electronic circuits. When such connections are shown, it should be understood that such connections are merely illustrative and are intended to show a capability for providing such connections and should not be considered limiting to the scope of the claims.
Likewise, although the Figures and aspects of the disclosure may show or describe devices herein as having a particular shape, it should be understood that such shapes are merely illustrative and should not be considered limiting to the scope of the techniques described herein. For example, the techniques described herein may be implemented in any shape or geometry for any material or layer to achieve desired results. In addition, examples in which two transistors or devices are shown stacked on top of one another are shown for illustrative purposes only, and for the purposes of simplicity. Indeed, the techniques described herein may provide for one to any number of stacked devices.
The panel 100 may be polished via a rotating polishing pad (not depicted), which can be larger than or smaller than the panel 100. Where the polishing pad is larger than the panel along at least one axis, an effective contact portion of the pad is defined according to a circumscription of the panel 100 (that is, such a portion of the pad will cross over at least some portion of the panel 100). A depicted circumscription line 102 indicates such a contact portion. Although the circumscription line 102 is provided as circular, the pad itself can take various forms, such as circular, hexagonal, oblong, or so forth. An inner portion 104 of the panel 100 (interior to an inscription line 106) may receive relatively constant pressure from a flush polishing pad. However, outer portions 108 of the panel 100 (disposed exterior to the inscription line 106) can receive uneven polishing. For example, as a portion of the pad passes over the edges of the panel 100, transitioning between non-contact with the panel 100 and contact with the panel 100, the polishing can round the edges or otherwise apply uneven forces. Such transitions can impact the outer portions 108 of the panel 100 by rounding edges (particularly along a leading edge of a relative direction of rotation 110). Moreover, such transition forces can displace the panel 100 within a retention mechanism (e.g., retention ring or rectangular retention assembly) and thus impact an inner portion of the panel 100.
In some embodiments, the polishing pad is smaller than the panel 100, and is moved along the surface of the panel 100 to polish a panel surface. As in the case of the large pad though, while polishing the outer portions 108 of the panel, a smaller pad will nonetheless transition between contact with the panel 100 and non-contact with the panel 100. The movement of either of the panel 100 or the polishing pad refers to movement of one relative to the other. According to some embodiments, both of the panel 100 or the pad are rotated or otherwise moved. According to some embodiments, one or the other of the panel 100 or the pad are maintained in a fixed position and the other of the panel 100 or the pad are moved (e.g., rotated).
The effects of the transition of contact with the panel 100 and non-contact with the panel 100 can vary according to a pressure applied between the pad and the panel 100. For example, a low-contact pressure (e.g., less than one pound per square inch, PSI) can reduce asymmetries related to the transition, relative to higher contact pressures, as may be associated with chemical-mechanical grinding or polishing (CMP/G) processes. Accordingly, a chemical process can be used to planarize copper, or dielectric (e.g., organic dielectrics or high-k dielectrics) to form a patterned conductive layer (e.g., the RDL). Such an approach may be used to planarize layers of an RDL or other layers of the panel 100 without incurring edge rounding or other asymmetries/effects associated with CMP/G processes.
In various embodiments, operations of the method 400 may be associated with top, cross-sectional, perspective, or other views of an example semiconductor device 300 at various fabrication stages as shown in at least
The method 400 includes but is not limited to operations 402-414. At operation 402, the method 400 includes providing a polygonal panel 100. The polygonal panel 100 can include a material for a substrate of an interposer. For example, the polygonal panel can include or consist substantially of silicon oxides, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG) such as fused silica glass, the like, or combinations thereof.
Corresponding to operation 404 of
At operation 404, the method 400 includes patterning a first dielectric layer 502. The dielectric layer 502 can includes a silicon oxide such as silicon dioxide, or an organic material. For example, the organic material can include polyimide, epoxy resin, or bismaleimide-triazine (BT) resin. The first dielectric layer 502 may be deposited over the surface of a substrate panel 100 using an appropriate technique such as vapor deposition including, for example: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), as well as other plasma processes such as plasma enhanced CVD (PECVD), and other processes such as sputtering or epitaxial growth from a seed layer.
A patterning layer (e.g., a layer including a patternable material such as a photoresist 504) can be formed over the surface of the interposer 302. For example, a mask may be deposited by spin coating a photoresist material over the dielectric layer 502. In various implementations, the mask is patternable using a series of techniques including lithograph (e.g., photolithography) and etching. Generally, the mask can be patterned by exposing (or irradiating) the photoresist material to a suitable light source (e.g., ultraviolet (UV), extreme ultraviolet (EUV), etc.) through a photomask and developing the exposed photoresist layer to form a patterned mask. The developing process removes portion(s) of the exposed photoresist layer based on chemical interactions between the exposed photoresist material and a solvent (e.g., a developer) used during the developing process. The patterned mask may then be used to further process (e.g., etch) the underlying dielectric layer 502. For example, the pattered mask may be used to etch the dielectric layer 502 using a suitable etching process to realize the depicted view 500. After processing the dielectric layer 502, the patterned mask may be removed by a suitable method, such as resist stripping or plasma ashing.
Corresponding to operation 406 of
At operation 406, the method 400 includes depositing a conductive layer 602 over the interposer 302 to form a first conductive layer 602. Operation 406 can include one or more sub-operations. For example, in some embodiments, the conductive layer 602 can be deposited in a direct plating operation. In some embodiments, the conductive layer 602 can be deposited according to a first seed layer operation and subsequent plating operation, adhering to the seed layer.
As is depicted, the first conductive layer 602 can occupy the openings formed at operation 404, and extend over the remaining portions of the dielectric layer 502. This overfill of the openings can avoid voids or incomplete fill of the openings. However, since the conductive layer 602 in the various openings can electrically connect along the conductive material formed over the dielectric layer 502, a further process may be necessitated to electrically disconnect the conductive material (e.g., the copper) in the various openings from one-another. More particularly, a planarization process may such as a chemical polishing process can be employed.
Such an approach can diverge from other techniques used for forming RDL layers 312 or other layers over an interposer 302. For example, other techniques can deposit the photoresist 504 of the mask layer over the substrate itself without depositing or etching the openings in a dielectric layer 502. Thereafter, a conductive layer (e.g., copper) can be selectively deposited into openings defined according to the patterned layer itself. Accordingly, a conductive layer can be laterally defined according to the patterned layer itself rather than the openings formed in a dielectric layer 502 based on the patterned layer, as is depicted with regard to the first conductive layer 602 of
With continued reference to the other techniques not depicted herein, conductive layer height can be defined according to an amount of material deposited rather than according to a planarization operation 408. However, line and space dimensions of these alternative techniques may exhibit greater minimum features sizes, relative to the approaches provided herein (e.g., greater than two micrometers, relative to less than one micrometer).
Corresponding to operation 408 of
At operation 408, the method 400 includes planarizing the upper surface of the interposer 302. More particularly, a chemical polishing process may be employed to planarize the upper surface. Such a chemical polishing process can use pressures of less than one PSI between a polishing pad 202 and the interposer 302 (e.g., a panel 100 of interposers 302, as depicted in
According to some implementations, a liquid is provided that may have an etching chemical and a passivating chemical. The liquid may be provided as embedded in a polishing pad 202 or separately therefrom. The etching chemical is anything that can corrode a copper or other material of the conductive layer 602 such as peroxides or hydroxides. The etching chemical may or may not also be selective to the dielectric layer 502, according to various embodiments. The passivating chemical can convert an oxide of the conductive layer (e.g., copper oxide) into a new form, such as may be used to create a surface coating. Such a passivating chemical can include benzotriazole (BTA). The chemical can be continuously added to the surface of the panel 100 to be polished during this process, either by the pad 202 or external thereto. The polishing pad 202 can strip the protecting layer through some method such as the contact or application of an additional chemical that can act on a copper oxide or copper nitride film. An alternative route is to use only one chemical in the pad 202 to directly strip material only when the pad 202 is contacting the conductive layer 602. A fluid such as water may be provided and removed during or after the process to carry away material during a rinsing process.
Additionally or alternatively, another chemical may be included to decrease static etch rate. Instead of altering the surface to passivate it (e.g., with BTA) the surface of the panel 100 may be coated with a protective film. Some examples of surfactants as pay form such a film include sodium dodecyl sulphate (SDS) and cetyltrimethyl ammonium bromide (CTAB).
For glass panels 100, one implementation includes spinning only the polishing pad 202. Although a larger polishing pad 202 may be used, at some point, if the pad 202 is very large, leading edge/trailing edge issues can present, as discussed above. The use of a polishing pad 202 that is smaller in lateral dimension or surface area than the panel can eliminate or mitigate such effects. For example, the pad can be at least fifty percent smaller or at least seventy-five percent smaller than the panel 100. The polishing pad 202 is moved (e.g., laterally or rotationally) along and across the surface of the panel 100. An advantage of the smaller pad size is the ability to customize the polishing process depending on the level of polishing needed. Moreover, since the pressure of the polishing pad 202 is generally low (e.g., less than one PSI, potentially approaching zero), the process is less likely to damage large glass panels 100, which can reach 500 millimeters by 500 millimeters in dimension, or larger.
Corresponding to operations 410-414 of
At operation 410, the method 400 includes patterning vertical interconnect openings in a second dielectric layer 802. The second dielectric layer 802 can be formed over the planarized surface of the interposer 302 according to any of the techniques described above with regard to the first dielectric layer 502 of operation 404. The openings can be formed in the second dielectric layer 802 according to the any of the techniques described above with regard to the openings of operation 404, such as via a patterned layer (e.g., photoresist). For example, the openings of operation 410 can correspond to an opening for vertical interconnects 806 of the conductive layer 804 of operation 414, as may be incorporated into an RDL layer 312 of an RDL structure of the interposer 302 for a semiconductor device 300.
At operation 412, the method 400 includes further patterning the second dielectric layer 802 to form lateral interconnect openings. These openings can be formed in the second dielectric layer 802 according to the any of the techniques described above with regard to the openings of operation 404 or 410, such as via a patterned layer (e.g., photoresist). For example, the openings of operation 410 can correspond to an opening for horizontal interconnects 808 of the conductive layer 804 of operation 414, as may be incorporated into a same RDL layer 312 as discussed above with regard to operation 410.
At operation 414, the method 400 includes forming a conductive layer. The conductive layer 804 is formed within the openings of operations 410 and 412, to form a conductive structure (e.g., conductive elements of an RDL layer 312). Operations 408 to 414 can be repeated to form further layers of an RDL structure. For example, an RDL structure can include three RDL layers 312, four RDL layers 312, five RDL layers 312, or so forth. Upon forming all the layers of the RDL structure, the upper surface may be planarized (as is depicted in
Referring now to
In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.
Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
“Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.
Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.
This application claims priority to and the benefit of U.S. Provisional Application No. 63/611,375, filed Dec. 18, 2023, which is incorporated herein by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63611375 | Dec 2023 | US |
