Patent Application
20170082689
A Single Event Upset (SEU) is a change in state or a transient voltage pulse at sensitive nodes in integrated circuits, such as processors. SEUs occur due to high energy particle strikes on the silicon substrate of processors. Errors can occur due to an SEU if it leads to a state flip in the sequential storage elements that determine the architectural state of the processor, such as the random access memory (RAM) arrays, the Register File and the architectural-state registers. An SEU can cause the affected integrated circuit to malfunction. Integrated circuits tend to become more susceptible to SEUs as integrated circuit feature sizes decrease, which is one of the more important trends in integrated circuit fabrication.
Generally, error detection cyclic redundancy checking (EDCRC) and scrubbing circuitry is used to perform SEU detection and correction in an integrated circuit. However, such circuitry requires complex detection circuitry and power to perform the SEU detection. It also takes a long time to detect the SEUs since the EDCRC and scrubbing circuitry needs to scan the entire IC for errors. This causes the EDCRC and scrubbing circuitry to be constantly running on the IC, which may result in higher power consumption and voltage supply noises.
In accordance with the present invention, systems and methods are provided for particle detection and corresponding error correction in an integrated circuit.
It is appreciated that the present invention can be implemented in numerous ways, such as a process, an apparatus, a system, or a device. Several inventive embodiments of the present invention are described below.
An integrated circuit having a substrate and logic circuitry that includes a group of transistors formed at a surface of the substrate is disclosed. The integrated circuit includes particle sensing circuitry formed below at least one transistor of the group of transistors. The particle sensing circuitry may detect a cosmic particle that passes through the logic circuitry. The particle sensing circuit may include a diode circuit that collects charges generated by the cosmic particle. The integrated circuit further includes a particle validation circuit that generates an error detection signal in response to detecting the cosmic particle with the particle sensing circuitry. The error detection signal may indicate that an error has occurred in the integrated circuit.
An integrated circuit having a surface and at least one transistor formed at the surface is disclosed. The integrated circuit includes error detection circuitry below the surface of the integrated circuit. The error detection circuitry detects charge generated by an atomic particle that passes through the integrated circuit. The integrated circuit further includes monitoring circuitry that identifies a particle energy associated with the atomic particle and that identifies error events in the integrated circuit based on the charge detected by the error detection circuitry. The monitoring circuitry may generate an error correction signal that activates error checking circuitry to perform corrective operations on error events associated with the atomic particle in the integrated circuit.
A method of operating an integrated circuit having a substrate with a substrate surface is disclosed. The method includes detecting stray charge generated by a particle passing through the integrated circuit with a particle sensing circuit. The particle sensing circuit may be embedded below the substrate surface of the integrated circuit. The method further includes correcting an error event in the integrated circuit by determining whether a voltage perturbation associated with the detected stray charge using monitoring circuitry connected to the particle sensing circuit. The monitoring circuitry may selectively correct the error events based on the identified particle energy.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The embodiments provided herein include systems and methods for atomic particle detection and error correction in an integrated circuit.
It will be obvious, however, to one skilled in the art, that the present exemplary embodiments may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail in order not to obscure unnecessarily the present embodiments.
Integrated circuit 10 contains volatile memory elements 20 that can be loaded with configuration data (also called programming data) using IO pins 14 and IO circuitry 12. Once loaded, the memory elements each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic 18. If desired, memory elements 20 may be used in SRAM-type memory arrays (e.g., to store data for processing circuitry during operation of integrated circuit 10).
Each memory element 20 may be formed from a number of transistors configured to form a bistable circuit. With one suitable approach, complementary metal-oxide-semiconductor (CMOS) integrated circuit technology is used to form the memory elements 20, so CMOS-based memory element implementations are described herein as an example. If desired, other integrated circuit technologies may be used to form the memory elements and the integrated circuit in which the memory elements are used to form memory arrays.
The memory elements may be loaded from an external erasable-programmable read-only memory and control chip or other suitable data source via IO pins 14 and IO circuitry 12. Loaded CRAM memory elements 20 may provide static control signals that are applied to the terminals (e.g., gates) of circuit elements (e.g., metal-oxide-semiconductor transistors) in programmable logic 18 to control those elements (e.g., to turn certain transistors on or off) and thereby configure the logic in programmable logic 18. The circuit elements may be transistors such as pass transistors, parts of multiplexers, look-up tables, logic arrays, AND, OR, NAND, and NOR logic gates, etc.
The memory elements 20 may be arranged in an array pattern. During programming operations, the array of memory elements may be provided with configuration data by a user (e.g., a logic designer). Once loaded with configuration data, the memory elements 20 selectively control portions of the circuitry in the programmable logic 18 and thereby customize its functions so that it will operate as desired.
The circuitry of integrated circuit 10 may be organized using any suitable architecture. As an example, the logic of integrated circuit 10 may be organized in a series of rows and columns of larger programmable logic regions each of which contains multiple smaller logic regions. The logic resources of integrated circuit 10 may be interconnected by interconnection resources 16 such as associated vertical and horizontal conductors. These conductors may include global conductive lines that span substantially all of integrated circuit 10, fractional lines such as half-lines or quarter lines that span part of integrated circuit 10, staggered lines of a particular length (e.g., sufficient to interconnect several logic areas), smaller local lines, or any other suitable interconnection resource arrangement. If desired, the logic of integrated circuit 10 may be arranged in more levels or layers in which multiple large regions are interconnected to form still larger portions of logic. Still other device arrangements may use logic that is not arranged in rows and columns.
When memory elements 20 are arranged in an array, horizontal and vertical conductors and associated loading circuitry may be used to load the memory elements with configuration data. Any suitable memory array architecture may be used to load an array of memory elements 20. One suitable arrangement is shown in
Memory cells that include memory elements such as memory elements 20 are prone to errors such as single event upsets (SEUs) that are sometimes also referred to as soft errors. An SEU occurs when a charged particle causes a transient voltage spike, which results in a change of state of the memory element. The charged particle may be due to natural radiation that is present in substrate of the integrated circuit and die packaging or generated in the substrate by cosmic rays or other atomic particles (e.g., alpha particles, neutron, and protons). One of the ways to detect the charged particle in the integrated circuit is by forming a particle sensing circuit (e.g., particle sensing circuits 202A, 202B, and 202C) under each transistor strip. As shown in
Accordingly, each particle sensing circuit 202A, 202B, and 202C may be connected to a corresponding particle validation circuit (e.g., particle validation circuits 206A, 206B, and 206C). In one embodiment, a particle validation circuit may sense the particle charge collected by a particle sensing circuit and generate an error detection signal that triggers error correction operations in integrated circuit 200. For example, particle validation circuits 206A, 206B, 206C may be sensor circuits. A more detailed description of transistor strip 220, particle sensing circuit 202A, and particle validation circuit 206A is described below with reference to integrated circuit region 230 of
As shown, transistors 321 and 322 may be subjected to an atomic particle (e.g., cosmic particle) strike, as indicated by arrow 315. The atomic particle may interfere with charges held within sensitive nodes of the transistors in the integrated circuit, thereby affecting the corresponding logic states. When high energy atomic particles strike a sensitive node region, the particles can cause a bit in the memory cell to change states or flip. These soft errors, which are also known as single event upsets (SEUs), generally affect storage elements, such as memory, latches and registers.
In order to detect the occurrence and location of the atomic particle strike (or single event) in the integrated circuit, a stray charge of the atomic particle may be collected and analyzed. To do so, a particle sensing circuit may be formed near the sensitive nodes of the transistors to collect the charge deposited by the atomic particle. As shown, particle sensing circuit 202A of height H is implanted below N-well 305 of a depth Z in substrate 203. In one embodiment, depth Z may correspond to a peak doping depth. Depth Z may be, for example, about 1.5 μm. Height H may be, for example, about 1 micrometer (μm). Particle sensing circuit 202A may also extend substantially in a horizontal plane in substrate 203, from N-well 305 of transistor 321 to the P-well region (not shown) of transistor 322. In one example, particle sensing circuit 202A may be a diode circuit.
To ensure that the atomic particle charge is electrically isolated from interfering signals (e.g., switching noises) in other wells, P-type implant regions may be formed surrounding N-well 305. A P-type implant region is represented by substrate 203 in
In one embodiment, the size of the particle sensing circuit may influence a detectable voltage perturbation from deposited charge of the atomic particle due to junction capacitance (i.e., capacitive effect at a junction of the particle sensing circuit). Larger particle sensing circuits may have greater junction capacitance than smaller particle sensing circuits, which may lead to smaller voltage perturbations from an atomic particle strike than when smaller particle sensing circuits are used. In an exemplary embodiment, to detect a neutron particle, a particle sensing circuit having a size of, for example, 1 μm in both width and height (denoted by H) and 13 millimeters (mm) in length (denoted by L), will have a voltage perturbation of about 30 millivolts (mV). In contrast, a particle sensing circuit having a size of, for example, 1 μm in both width and height (denoted by H) and 1 millimeters (mm) in length (denoted by L), will have a voltage perturbation of about 360 mV.
In another exemplary embodiment, to detect an alpha particle, a particle sensing circuit having a size of, for example, 1 μm in both width and height (denoted by H) and 0.04 millimeters (mm) in length (denoted by L), will have a voltage perturbation of about 30 millivolts (mV).
In contrast, a particle sensing circuit having a size of, for example, 1 μm in both width and height (denoted by H) and 0.01 millimeters (mm) in length (denoted by L), will have a voltage perturbation of about 110 mV.
The voltage perturbation from the deposited charge of the atomic particle can be detected by particle sensing circuit 202A as indicated by arrow 320. For example, particle validation circuit 206A may include a sensor circuit, such as a sense amplifier. Particle validation circuit 206A may generate an output signal (which may also be referred to as a sensor output), which is described later in
As shown in
Because transistors 321 and 322 can be potentially struck by a high-energy atomic particle, particle sensing circuit 202A may be provided in substrate 203 to detect the particle strike. As an example, assume that a particle strike occurs within transistor strip 210 (as indicated by arrow 315). A stray charge produced by the atomic particle may be deposited within sensitive nodes (e.g., N-well 305 of transistor 321) of transistor strip 210. In this scenario, particle sensing circuit 202A, which is implanted below transistors 321 and 322 in substrate 203, may collect the deposited charge from N-well 305.
Accordingly, particle validation circuit 206A may validate the collected charge from particle sensing circuit 202A by detecting a voltage perturbation from the deposited charge of the atomic particle as indicated by arrow 320. It should be appreciated that particle validation circuit 206A may be implemented either internally or externally to integrated circuit 200 of
In one embodiment, monitoring circuitry 403 may monitor a status of output signal 401 to identify a particle energy associated with the atomic particle and to identify error events in the integrated circuit. For example, monitoring circuitry 403 may include a polling circuit. In an embodiment, monitoring circuitry 403 may poll output signal 401 to determine whether a predetermined metric has changed, for example by comparing voltage perturbation output (e.g., output signal 401) to a predetermined voltage threshold. When the voltage perturbation output exceeds a predetermined threshold value, monitoring circuit 403 may generate an error correction signal (e.g., error correction signal 404) to error checking circuitry 405.
In general, error checking circuitry 405 may perform error detection and correction operations on the configuration RAM (CRAM) cells (e.g., memory elements 20 of
Illustrative steps involved in detecting and correcting soft error effects on an integrated circuit are shown in
During an atomic particle strike (as indicated by arrow 315 of
The deposited stray charge of the atomic particle is then collected by the particle sensing circuit at step 502. A particle validation circuit (e.g., particle validation circuit 206A of
At step 504, it is determined whether the voltage perturbation output is greater than a predetermined voltage threshold using the monitoring circuitry. As shown in
At step 506, a frequency of error checking operations is adjusted using error checking circuitry (e.g., error checking circuitry 405 of
The methods and apparatus described herein may be incorporated into any suitable circuit. For example, the methods and apparatus may be incorporated into numerous types of devices such as microprocessors or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPGAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), application specific integrated circuits (ASICs), just to name a few.
The programmable logic device described in one or more embodiments herein may be part of a data processing system that includes one or more of the following components: a processor; memory; IO circuitry; and peripheral devices. The data processing system can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any suitable other application where the advantage of using programmable or re-programmable logic is desirable. The programmable logic device can be used to perform a variety of different logic functions. For example, the programmable logic device can be configured as a processor or controller that works in cooperation with a system processor. The programmable logic device may also be used as an arbiter for arbitrating access to a shared resource in the data processing system. In yet another example, the programmable logic device can be configured as an interface between a processor and one of the other components in the system. In one embodiment, the programmable logic device may be one of the family of devices owned by the assignee.
Although the method operations were described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in a desired way.
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.
