Patent Application
20150357028
1. Field
Aspects of the present innovations relate generally to multi-bank memory circuitry, such as dual-pipe memory circuitry, and, more specifically, to systems and method involving capturing and propagating addresses and write data through multi-bank, dual-pipe memory circuitry.
2. Description of Related Information
In Quad-B2 SRAMs, by way of example, the two operations of a read and a write may be initiated per clock cycle, and two beats of data are transferred per operation per clock cycle (i.e. data transfers are DDR—double data rate).
As depicted in
A write operation is initiated by synchronously asserting the W# control pin “low” at the rising edge of the K input clock 102, by synchronously providing the write address on the A address pins at the rising of the K# input clock a half cycle later 104, by synchronously providing the first beat of write data on the D data pins at the rising edge of the KD input clock 105, and by synchronously providing the second beat of write data on the D data pins at the rising edge of the KD# input clock a half cycle later 106.
Note that K# input clock is the inverse of K input clock, and KD# input clock is the inverse of KD# input clock. K and K# are nominally 180 degrees out of phase, as are KD and KD#, but both pairs of clocks are allowed to have some amount of phase offset away from 180 degrees. KD/KD# can either be mesochronous with, or physically the same as, K/K#. When KD/KD# are mesochronous with K/K#, they are the same frequency and are generated from the same source clock, but are allowed to have some amount of phase offset.
In some instances, a Quad-B2 SRAM is architected as a multi-bank dual-pipe device (see U.S. patent application Ser. No. 13/327,721) such that, as pairs of read and write operations are initiated on a cycle-by-cycle basis, the pairs are processed alternately between two sets of pipelines operating at half the frequency of the SRAM clock. In the subsequent descriptions, the letters “U” and “V” are used to denote and distinguish between the two pipelines.
In order to facilitate the dual-pipe nature of various such implementation(s), and as illustrated in
The accompanying drawings, which constitute a part of this specification, illustrate various implementations and aspects of the innovations herein and, together with the description, help illustrate the principles of the present inventions. In the drawings:
Reference will now be made in detail to the inventions herein, examples of which are illustrated in the accompanying drawings. The implementations set forth in the following description do not represent all implementations consistent with the present inventions. Instead, they are merely some examples consistent with certain aspects related to the present innovations. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
Systems and methods for capturing read addresses, write addresses, and write data, and propagating them through dual, half-frequency pipelines to the memory array in multi-bank, dual-pipe Quad-B2 SRAMs are disclosed. Aspects of the present inventions relate to implementations for capturing pairs of read and write addresses, and propagating them to each memory bank through two distinct address input pipelines, each of which operates at half of the external clock frequency of the SRAM. According to some implementations, two beats of write data are captured and transferred per write operation, and are propagated to the each memory bank through two distinct data input pipelines, each of which operates at half of the external clock frequency of the SRAM. Various details on different implementations are set forth below.
At each memory bank, the bank address portion of the read and write address streams from the two address input pipelines are used to determine if the associated read and/or write operation(s) are targeted for that particular bank.
At each memory bank, the non-bank address portion of the read U and write V addresses from the two address input pipelines are used to select the particular location(s) within the bank to be read and/or written, if the associated read and/or write operation(s) are targeted for that particular bank, as determined by the bank address portion of the read and write addresses.
At each memory bank, the appropriate two beats of write data from the two data input pipelines are selected to be stored in the particular location within the bank, as determined by the non-bank address portion of the write addresses, if the associated write operation is targeted for that particular bank, as determined by the bank address portion of the write addresses.
A host 10 may include a memory controller 15 (e.g., a SRAM controller in this example) configured to communicate with the memory circuitry 20. For example, as explained in greater detail below, memory controller 15 may send first read control R#32 and/or first write control W#34 signals to R/W control circuitry 30, address signal A 42 to address circuitry 40, data signal D 52 to write data circuitry 50, input clock signals KD 54 and/or KD#56 to write data circuitry 50, and/or input clock signals K 62 and/or K#64 to one or more of R/W control circuitry 30, address circuitry 40, write data circuitry 50, and clock circuitry 60.
R/W control circuitry 30, address circuitry 40, write data circuitry 50, and/or clock circuitry 60 may communicate with one another, and address circuitry 40 and/or write data circuitry 50 may communicate with the multi-bank memory array 70. For example, as explained in greater detail below, clock circuitry 60 may supply clock signals Ku 66, Ku#68, Kv 72, and/or Kv#74 to write data circuitry 50 and/or address circuitry 50. Additionally, R/W control circuitry 30 may send read and/or write control signals 36 to address circuitry 40. Address circuitry 40 may send address location data Au 44 and/or Av 46 to the multi-bank memory array 70 to specify memory addresses to be read out or written. Write data circuitry may send write data D0u 76, D0v 78, D1u 82, and/or D1v 84 to the multi-bank memory array 70.
For example, a multi-bank, dual-pipe SRAM device may include a memory array operating a memory array frequency and comprising a plurality of SRAM banks, each SRAM bank includes a block of single port SRAM memory cells organized as a matrix of rows and columns and memory cell access circuitry. The plurality of SRAM banks may be simultaneously active. The memory cell access circuitry may include a first read control input and a first write control input for initiating read and write operations in the same clock cycle for each and every clock cycle. The memory cell access circuitry may also include a first input clock and a second input clock, wherein the second input clock is the inverse of the first input clock.
In some embodiments, the access circuitry may be configured to designate alternating clock cycles as a first pipeline clock cycle and a second pipeline clock cycle respectively; generate a first pipeline clock and a second pipeline clock having periods twice that of the first and second input clocks, wherein the first pipeline clock is high during the first pipeline clock cycles and the second pipeline clock is the inverse of the first pipeline clock; and generate a third pipeline clock and a fourth pipeline clock having periods twice that of the first and second input clocks, where the third pipeline clock is high during the second pipeline clock cycle and the fourth pipeline clock is the inverse of the third pipeline clock.
In some embodiments, a read operation initiated in any clock cycle may be paired with a write operation initiated in the same clock cycle, and the read operation and the write operation may be executed sequentially over two clock cycles, either to a same SRAM bank or to a different SRAM bank. The read operation may be executed for less than two cycles, the write operation may be executed for less than or equal to a duration of one cycle, and a combined duration of the read operation and the write operation may not exceed two cycles.
The first data input pipeline DIPu 302 and the second data input pipeline DIPv 303 may be used to latch the two beats of write data and de-multiplex them into separate U beat one, U beat two, V beat one, and V beat two write data streams D0u, D1u, D0v, and D1v that may be bussed to each memory bank 321.
At each memory bank, a 2:1 mux 311 may select which addresses in the Au and Av read/write address streams are used to read and/or write the bank 321.
At each memory bank, one 2:1 mux 312 may select which beat one write data from the D0u and D0v write data streams is used to write the bank 321, and a second 2:1 mux 312 may be used to select which beat two write data from the D1u and D1v write data streams is used to write the bank 321.
Two examples of the first implementation are described below. In each example, the read operation initiated in a first U cycle may be paired with a write operation initiated in a first U cycle (although not necessarily the same first U cycle), and the two operations may be executed sequentially over two cycles, either to the same memory bank or to different banks. In conjunction, the associated read and write addresses may propagate to each memory bank 321 through the first address input pipeline AIPu 301 and the 2:1 A Mux 321, and the associated write data may propagate to each memory bank 321 through the first data input pipeline DIPu 303 and a 2:1 D Mux 312.
The read operation initiated in a second V cycle may be paired with a write operation initiated in a second V cycle (although not necessarily the same second V cycle), and the two operations may be executed sequentially over two cycles, either to the same memory bank or to different banks. In conjunction, the read and write associated addresses may propagate to each memory bank 321 through the second address input pipeline AIPv 302 and the 2:1 A Mux 321, and the associated write data may propagate to each memory bank 321 through the second data input pipeline DIPv 304 and a 2:1 D Mux 312.
The AIPu/v and DIPu/v implementations may differ based on inclusion/exclusion of write buffering. The address and data multiplexing at each memory bank may be the same for both implementations.
Note that because pairs of read and write operations may be executed over two cycles, yet pairs of read and write operations may be initiated every cycle, one or two memory banks may be busy (i.e. in the midst of being accessed) when a new pair of read and write operations is initiated. The user may operate the memory to avoid “bank conflicts”—i.e. to avoid reading banks that are busy due to previous read and write operations.
Note also that, with aspects of the innovations herein, when a read and write operation initiated to the same bank are executed sequentially over two cycles, each operation may not necessarily be executed within one cycle. Rather, the read operation may be executed in greater than one cycle, and the write operation may be executed in less than one cycle, provided the combined duration of both operations is no greater than two cycles, for example. This concept is illustrated in
A first example is described below of an implementation without write buffering for each of the address input and data input. With respect to the address input as illustrated in
The three registers in the read address path may be implemented in two stages. Stage one may include one register RA 401 that may use the rising edge of first clock K 62 to capture the read address every cycle, regardless of whether first read control R#32 is captured “low” or “high” at that clock edge; consequently the captured address may be unused if a read operation is not initiated in the cycle. Stage two may include two registers RAu 421 and RAv 422. RAu 421 may use the rising edge of first pipeline clock Ku 66 to re-latch the read address from RA 401, thereby generating a U read address that may remain valid for two clock cycles. RAv 422 may use the rising edge of third pipeline clock Kv 72 to re-latch the read address from RA 401, thereby generating a V read address that may remain valid for two clock cycles.
The three registers in the write address path may be implemented in two stages. The stage one path may include one register WA 402 that may use the rising edge of second input clock K#64 to capture the write address. In one embodiment, the rising edge of second input clock K#64 may be used only in cycles in which first write control W 86 is captured “low” at the previous rising edge of first input clock K 62; consequently the captured write address may always be used, and power may be saved in those cycles in which write operations are not initiated. Stage two may include two registers WAu 423 and WAv 424. WAu 423 may use the rising edge of second pipeline clock Ku#68 to re-latch the write address from WA 402, thereby generating a U write address that may remain valid for two clock cycles. WAv 424 may use the rising edge of fourth pipeline clock Kv#74 to re-latch the write address from WA 402, thereby generating a V write address that may remain valid for two clock cycles.
The first mux Mu 441 may be used to time-multiplex the U read and write addresses into a single U read/write address stream AU that may be bussed to each memory bank 321. First pulse Ru 451 may be a one-shot pulse derived from first pipeline clock Ku 66 that may cause the U read address to be selected, and may be shorter than one cycle at slow operating frequency, or longer than one cycle at maximum operating frequency. Second pulse Wu 461 may be a one-shot pulse derived from Kv 72 when Ru 451 is shorter than one cycle, or self-timed from Ru 451 completed when Ru 451 is longer than one cycle, causing the U write address to be selected. In other words, Wu 461 may be a one-shot pulse derived from the logical function of “NOT(Ru) AND Kv”. Like with the WA 402 register, one implementation may provide that Wu only goes active when a write operation is initiated in a U cycle (i.e. when W 86 is captured “low” at the rising edge of K 62 in a U cycle); consequently, Au may only change from a U read address to a U write address if a write operation is initiated, and power may be saved in those cycles in which a write operation is not initiated.
The second mux Mv 442 may be used to time-multiplex the V read and write addresses into a single V read/write address stream AV that may be bussed to each memory bank 321. Third pulse Rv 452 may be a one-shot pulse derived from third pipeline clock Kv 72 that may cause the V read address to be selected, and may be shorter than one cycle at slow operating frequency, or longer than one cycle at maximum operating frequency. Fourth pulse Wv 462 may be a one-shot pulse derived from Ku 66 when Rv 452 is shorter than one cycle, or self-timed from Rv 452 completed when Rv 452 is longer than one cycle, causing the V write address to be selected. In other words, Wv 462 may be a one-shot pulse derived from the logical function of “NOT(Rv) AND Ku”. Like with the WA 402 register, one implementation may provide that Wv 462 only goes active when a write operation is initiated in a V cycle (i.e. when W 86 is captured “low” at the rising edge of K 62 in a V cycle); consequently, Av may only change from a V read address to a V write address if a write operation is initiated, and power may be saved in those cycles in which a write operation is not initiated.
In some implementations, registers RA 401, Rau 421, WA 402, WAu 423 and mux Mu 441 may comprise the AIPu 301, and registers RA 401, RAv 422, WA 402, WAv 424 and mux Mv 442 may comprise the AIPv 302.
In such implementations, the read initiated in any U cycle may be paired with the write initiated in the same U cycle. The read initiated in any V cycle may be paired with the write initiated in the same V cycle.
Note that in
In another implementation, eight registers (or latches) may be used to implement the DIPu and DIPv. As depicted in
The four registers in the beat one write data path may be implemented in three stages. Stage one may include one register D0KD 501 that may use the rising edge of first data input clock KD 54 to capture the beat one write data every cycle, regardless of whether W# is captured “low” or “high” at the rising edge of first input clock K 62 in the same clock; consequently the captured data may be unused if a write operation is not initiated in the cycle.
Stage two may include one register D0K 511 that may use the rising edge of second input clock K#64 to re-latch the beat one write data from D0KD 501, thereby transferring the data from the first data input clock KD 54 clock domain to the first input clock K 62 clock domain.
Stage three may include two registers D0Ku 521 and D0Kv 522. D0Ku 521 may use the rising edge of third pipeline clock Kv 72 to re-latch the beat one write data from D0KD 501, thereby generating a U beat one write data that may remain valid for two clock cycles. D0Kv 522 may use the rising edge of first pipeline clock Ku 66 to re-latch the beat one write data from D0K 511, thereby generating a V beat one write data that may remain valid for two clock cycles.
The four registers in the beat two write data path may be implemented in three stages. Stage one may include one register D1KD 502 that may use the rising edge of the first data input clock KD#56 to capture the beat two write data every cycle, regardless of whether W# is captured “low” or “high” at the rising edge of first input clock K 62 in the same cycle; consequently the captured data may be unused if a write operation is not initiated in the cycle.
Stage two may include one register D1K 512 that may use the rising edge of the first input clock K 62 to re-latch the beat two write data from D1KD 502, thereby transferring the data from the first data input KD clock domain to the K clock domain.
Stage three may include two registers D1Ku 523 and D1Kv 524. D1Ku may use the rising edge of third pipeline clock Kv 72 to re-latch the beat two write data from D1K 512, thereby generating a U beat two write data that may remain valid for two clock cycles. D1Kv 524 may use the rising edge of first pipeline clock Ku 66 to re-latch the beat two write data from D1K 512, thereby generating a V beat two write data that may remain valid for two clock cycles.
Together, in some implementations, registers D0KD 501, D0K 511, D0Ku 521, D1KD 502, D1K 512, and D1Ku 523 may comprise the DIPu, and registers D0KD 501, D0K 511, D0Kv 522, D1KD 502, D1K 512, and D1Kv 524 may comprise the DIPv.
Note that the implementations of stages one and two in the write data paths may allow for the first data input clock KD 54 clock edges to lead or trail the corresponding K 62 clock edges by approximately a half cycle.
Note that in this example, each new read operation (in one pipe) overlaps with both the read and the write operations from the previous cycle (in the other pipe), as illustrated by the overlapping Au 441 and Av 442 addresses in
Another implementation is provided below with write buffering features. Write buffering may be facilitated by inserting additional register (or latch) stages (referred to as “write buffers”) in the write address and write data paths such that write operations are executed some number of cycles after they are initiated, for example.
Address Input Aspects Any number of write buffers greater than or equal to one may be inserted in the first address input pipeline AIPu and second address input pipeline AIPv after the write address is split into the U and V pipelines.
As illustrated in
In one implementation, the three registers in the read address path may be implemented in two stages, similar to
In some implementations, the seven registers in the write address path may be implemented in four stages. Stage one may include one register WA 802 similar to WA 402 in
Stage two may include two registers WAB1u 823 and WAB1v 824. WAB1u 823 may be the first “write buffer” inserted in the write address path of the AIPu. WAB1u 823 may use the rising edge of third pipeline clock Kv 72 to re-latch the write address from WA 802, thereby generating a U write address that may remain valid for two clock cycles. WAB1v 824 may be the first “write buffer” inserted in the write address path of the AIPv. WAB1v 824 may use the rising edge of the first pipeline clock Ku 66 to re-latch the write address from WA 802, thereby generating a V write address that may remain valid for two clock cycles.
Stage three may include two registers WAB2u 825 and WAB2v 826. WAB2u 825 may be the second “write buffer” inserted in the write address path of the address input pipeline AIPu. WAB2u 825 may use the rising edge of third pipeline clock Kv 72 to re-latch the write address from WA 802, thereby generating a U write address that may remain valid for two clock cycles. WAB2v 826 is the second “write buffer” inserted in the write address path of the AIPv. WAB2v 826 may use the rising edge of the first pipeline clock Ku 66 to re-latch the write address, thereby generating a V write address that may remain valid for two clock cycles.
Stage four may include two registers WAu 827, and WAv 828. WAu 827 may be the last register in the write address path of the address input pipeline AIPu. WAu 827 may be functionally equivalent to WAu 423 in
The two muxes Mu 841 and Mv 842 may be functionally identical to Mu 441 and Mv 442 in
Together, registers RA 801, Rau 821, WA 802, WAB1u 823, WAB2u 825, WAu 827 and mux Mu 841 may comprise the AIPu, and registers RA 801, RAv 822, WA 802, WAB1v 824, WAB2v 826, WAv 828 and mux Mv 842 may comprise the AIPv.
In this implementation, the read initiated in any U cycle may be paired with the write initiated in the U cycle from four cycles previously. The read initiated in any V cycle may be paired with the write initiated in the V cycle from four cycles previously.
Note that in
Any number of write buffers greater than or equal to one may be inserted in the DIPu and DIPv after the two beats of write data are split into the U and V pipelines, but the number inserted must be the same as the number inserted in the AIPu and AIPv so that write data remains aligned with its associated write address.
Such features are illustrated by way of example in
As depicted in
According to one illustrative implementation, for example, the eleven registers in the beat one write data path may be implemented in eight stages.
Stage one may include one register D0KDa 1001 similar to D0KD 501 in
Stage two may include one latch D0KDb 1003. D0KDb 1003 may use the second data input clock KD#56 to re-latch the beat one write data from D0KDa 1001. The latch may be transparent while KD#56 is “low”, and may latch when KD#56 goes “high”.
Stage three may include one latch D0Ka 1011 that may use K#64 to re-latch the beat one write data from D0KDb 1003, thereby transferring the data from the first data input clock KD 54 clock domain to the input clock K 62 clock domain. The latch may be transparent while K#64 is “low”, and may latch when K#64 goes “high”.
Stage four may include one latch D0Kb 1013. D0Kb may use K 62 to re-latch the beat one write data from D0Ka 1011. The latch may be transparent while K 62 is “low”, and may latch when K 62 goes “high”.
Stage five may include one latch D0Kc 1015 that may use K#64 to re-latch the beat one write data from D0Kb 1013. The latch may be transparent while K#64 is “low”, and may latch when K#64 goes “high”.
Stage six may include two registers D0B1u 1021 and D0B1v 1022. D0B1u 1021 may be the first “write buffer” inserted in the beat one write data path of the DIPu. D0B1u 1021 may use the rising edge of fourth pipeline clock Kv#74 to re-latch the beat one write data from D0Kc 1015, thereby generating a U beat one write data that may remain valid for two clock cycles. D0B1v 1022 may be the first “write buffer” inserted in the beat one write data path of the DIPv. D0B1V 1022 may use the rising edge of the second pipeline clock Ku#68 to re-latch the beat one write data from D0Kc 1015, thereby generating a V beat one write data that may remain valid for two clock cycles.
Stage seven may include two registers D0B2u 1031 and D0B2v 1032. D0B2u 1031 may be the second “write buffer” inserted in the beat one write data path of the DIPu. D0B2u 1031 may use the rising edge of the third pipeline clock Kv 72 to re-latch the beat one write data from D0B1u 1021, thereby generating a U beat one write data that may remain valid for two clock cycles. D0B2v 1032 may be the second “write buffer” inserted in the beat one write data path of the DIPv. D0B2v 1032 may use the rising edge of first pipeline clock Ku to re-latch the beat one write data from D0B1v 1022, thereby generating a V beat one write data that may remain valid for two clock cycles.
Stage eight may include two registers D0Ku 1041 and D0Kv 1042. D0Ku 1041 may be the last register in the beat one write data path of the DIPu. D0Ku 1041 may be functionally equivalent to D0Ku 521 in
The ten registers in the beat two write data path may be implemented in seven stages. Stage one may include one register D1KDa 1002 that may be similar to D1KD 502 in
Stage two may include one latch D1KDb 1004 that may use first data input clock KD 54 to re-latch the beat two write data from D1KDa 1002. The latch may be transparent while KD 54 is “low”, and may latch when KD 54 goes “high”.
Stage three may include one latch D1Kb 1014 that may use first input clock K 62 to re-latch the beat two write data from D1KDb 1004, thereby transferring the data from the KD 54 clock domain to the K 62 clock domain. The latch may be transparent while K 62 is “low”, and may latch when K 62 goes “high”.
Stage four may include one latch D1Kc 1016 that may use second input clock K#64 to re-latch the beat two write data from D1Kb 1014. The latch may be transparent while K#64 is “low”, and may latch when K#64 goes “high”.
Stage five may include two registers D1B1u 1023 and D1B1v 1024. D1B1u 1023 may be the first “write buffer” inserted in the beat two write data path of the DIPu. D1B1u 1023 may use the rising edge of fourth pipeline clock Kv#74 to re-latch the beat two write data from D1Kc 1016, thereby generating a U beat two write data that may remain valid for two clock cycles. D1B1v 1024 may be the first “write buffer” inserted in the beat two write data path of the DIPv. D1B1v 1024 may use the rising edge of second pipeline clock Ku#68 to re-latch the beat two write data from D1Kc 1016, thereby generating a V beat two write data that may remain valid for two clock cycles.
Stage six may include two registers D1B2u 1033 and D1B2v 1034. D1B2u 1033 may be the second “write buffer” inserted in the beat two write data path of the DIPu. D1B2u 1033 may use the rising edge of third pipeline clock Kv 72 to re-latch the beat two write data from D1B1u 1023, thereby generating a U beat two write data that may remain valid for two clock cycles. D1B2v 1034 may be the second “write buffer” inserted in the beat two write data path of the DIPv. D1B2u 1034 may use the rising edge of first pipeline clock Ku 66 to re-latch the beat two write data from D1B1v 1024, thereby generating a V beat two write data that may remain valid for two clock cycles.
Stage seven may include two registers D1Ku 1043 and D1Kv 1044, where D1Ku 1043 may be the last register in the beat two write data path of the DIPu. D1ku 1043 may be functionally equivalent to D1Ku 523 in
Together, registers D0KDa 1001, D0KDb 1003, D0Ka 1011, D0Kb 1013, D0Kc 1015, D0B1u 1021, D0B2u 1031, D0Ku 1041, D1KDa 1002, D1KDb 1004, D1Kb 1014, D1Kc 1016, D1B1u 1023, D1B2u 1033, and D1Ku 1043 may comprise the DIPu, and registers D0KDa 1001, D0KDb 1003, D0Ka 1011, D0Kb 1011, D0Kc 1015, D0B1v 1022, D0B2v 1032, D0Kv 1042, D1KDa 1002, D1KDb 1004, D1Kb 1014, D1Kc 1016, D1B1v 1024, D1B2v 1034, and D1Kv 1044 may comprise the DIPv.
Note that the implementations of stages one through five in the beat one write data path, and stages one through four in the beat two write data path, may allow for the KD 54 clock edges to lead or trail the corresponding K 62 clock edges by approximately half a cycle.
Note that in this example, each new read operation (in one pipe) overlaps with the read operation from the previous cycle (in the other pipe), and with the write operation from 5 cycles previously (in the other pipe), as illustrated by the overlapping Au 841 and Av 842 addresses in
As illustrated in
The address muxes depicted in
As illustrated in
D1u 1403 may be the beat two write data output by the DIPu 303 and may be an input to each bank's D1n Mux. D1v 1404 may be the beat two write data output by the DIPv 304 and may be an input to each bank's D1n Mux. D0n Mux 1431 may be the write data input mux that muxes D0u and D0v to bank “n”. D1n Mux 1432 may be the write data input mux that muxes D1u and D1v to bank “n”. D0(n) 1421 may be the output of the D0n Mux that provides beat one write data to bank “n”. D1(n) 1422 may be the output of the D1n Mux that provides beat two write data to bank “n”.
Au(BAn).WP 1411 may be a one-shot pulse generated from the decoded bank address bits from the Au write address that indicate bank “n” is to be written. When active, D0(n)=D0u and D1(n)=D1u. Av(BAn).WP 1412 may be a one-shot pulse generated from the decoded bank address bits from the Av write address that indicate bank “n” is to be written. When active, D0(n)=D0v and D1(n)=D1v.
The data muxes depicted in
Note that when operating at maximum frequency (as illustrated in
Some implementations of the present invention herein describe systems and methods for capturing pairs of read and write addresses, and propagating them to each memory bank through two distinct address input pipelines, each of which operates at half of the external clock frequency of the SRAM. The read and write control signals are captured and propagated to each memory bank. Two beats of write data are captured and transferred per write operation, and are propagated to each memory bank through two distinct data input pipelines, each of which operates at half of the external clock frequency of the SRAM. Details on different implementations are provided below.
At each memory bank, the bank address portion of the read and write addresses from the two address input pipelines are used to determine if the associated read and/or write operation(s) are targeted for that particular bank.
At each memory bank, the non-bank address portion of the read and write addresses from the two address input pipelines are used to select the particular location(s) within the bank to be read and/or written, if the associated read and/or write operation(s) are targeted for that particular bank (as determined by the bank address portion of the read and write addresses).
At each memory bank, the appropriate two beats of write data from the two data input pipelines are selected to be stored in the particular location within the bank (as determined by the non-bank address portion of the write addresses), if the associated write operation is targeted for that particular bank (as determined by the bank address portion of the write addresses).
At each memory bank, the Ain read/write address stream is de-multiplexed 1911 into separate U read, U write, V read, and V write addresses that are validated by the Rin and Win control signals. A 4:1 mux 1912 is used to select which of those addresses are used to read and/or write the bank.
At each memory bank, the Din write data stream is de-multiplexed 1913 into separate U beat one, U beat two, V beat one, and V beat two write data, one 2:1 mux 1914 selects which beat one write data is used to write the bank, and a second 2:1 mux 1914 selects which beat two write data is used to write the bank.
In this manner, the read operation initiated in a U cycle is paired with the write operation initiated in the same U cycle, and the two operations are executed sequentially over two cycles, either to the same memory bank or to different banks. In conjunction, the associated read and write addresses propagate to each memory bank 1921 through the AILM 1901, the U portion of the 1:4 A UN De-mux 1911, and the 4:1 A Mux 1912, the associated read and write control signals propagate to each memory bank 1921 through the CIL 1902, and the associated write data propagates to each memory bank 1921 through the DILM 1902, the U portion of the 1:4 DUN De-mux 1913, and a 2:1 D Mux 1914.
The read operation initiated in a V cycle is paired with the write operation initiated in the same V cycle, and the two operations are executed sequentially over two cycles, either to the same memory bank or to different banks. In conjunction, the associated read and write addresses propagate to each memory bank 1921 through the AILM 1901, the V portion of the 1:4 A UN De-mux 1911, and the 4:1 A Mux 1912, the associated read and write control signals propagate to each memory bank 1921 through the CIL 1902, and the associated write data propagates to each memory bank 1921 through the DILM 1902, the V portion of the 1:4 DUN De-mux 1913, and a 2:1 D Mux 1914.
Note that because pairs of read and write operations are executed over two cycles, yet pairs of read and write operations can be initiated every cycle, one or two memory banks may be busy (i.e. in the midst of being accessed) when a new pair of read and write operations is initiated. It is up to the user to avoid “bank conflicts”—i.e. to avoid reading banks that are busy due to previous read and write operations.
Note also that with the inventions herein, when a read and write operation initiated to the same bank are executed sequentially over two cycles, each operation isn't necessarily executed within one cycle. Rather, the read operation can be executed in greater than one cycle, and the write operation can be executed in less than one cycle, provided the combined duration of both operations is no greater than two cycles. This concept is illustrated in
Mux AM 2011 time-multiplexes the captured read and write addresses into a single read/write address stream Ain that is bussed to each memory bank. K clock “high” causes the read address to be selected (i.e. muxed into the Ain address stream), and K# clock “high” causes write address to be selected (i.e. multiplexed into the Ain address stream). Like with the WA 2002 register, one implementation is to use the rising edge of K# only in cycles in which the first write control W# is captured “low” at the previous rising edge of K; consequently Ain only changes from a read address to a write address if a write operation is initiated, and power is saved in those cycles in which a write operation is not initiated.
Six AND gates and six registers (or latches) are used to de-multiplex the bank (n) signal four ways, into separate U read, U write, V read, and V write bank (n) signals representing the 1:4 A UN De-mux 1911 of the bank addresses, and those four bank (n) signals are used to generate one U read, two U write, one V read, and two V write bank (n) clocks. Bank (n) is logically ANDed with Rin via AND gate 2211 to generate rbank (n), to ensure it is generated from a valid read address when it is subsequently latched by RBAnu or RBAnv.
Bank (n) is logically ANDed with Win via AND gate 2212 to generate wbank (n), to ensure it is generated from a valid write address when it is subsequently latched by WBAnu or WBAnv.
Exemplary configuration and control of the various registers (or latches) may be as follows, for this illustrative implementation. For example, register RBAnu 2221 may use the rising edge of the first pipeline clock Ku to capture rbank (n), thereby generating a U read bank (n) signal RBAu(n) that is active for two cycles. RBAu(n) is logically ANDed with a delayed version of Ku via AND gate 2231, thereby generating a U read bank (n) clock KRu(n). Register RBAnv 2222 may use the rising edge of the third pipeline clock Kv to capture rbank (n), thereby generating a V read bank (n) signal RBAv(n) that is active for two cycles. RBAv(n) is logically ANDed with a delayed version of Kv via AND gate 2232, thereby generating a V read bank (n) clock KRv(n). Register WBAnu 2223 may use the rising edge of the second pipeline clock Ku# to capture wbank (n), thereby generating a U write bank (n) signal WBAu(n) that is active for two cycles. WBAu(n) is logically ANDed with a delayed version of Ku# via AND gate 2233 to generate a first U write bank (n) clock KWu(n). Register WBA1nu 2243 may use the rising edge of the third pipeline clock Kv to re-latch KWu(n), thereby generating a second U write bank (n) clock KW1u(n). Register WBAnv 2224 may use the rising edge of the fourth pipeline clock Kv# to capture wbank (n), thereby generating a V write bank (n) signal WBAv(n) that is active for two cycles. WBAv(n) is logically ANDed with a delayed version of Kv# via AND gate 2234 to generate a first V write bank (n) clock KWv(n). Register WBA1nv 2244 may use the rising edge of the first pipeline clock Ku to re-latch KWv(n), thereby generating a second V write bank (n) clock KW1v(n).
Read U Self-Timed logic 2301 uses KRu(n) to generate a U read bank (n) pulse Ru(n) that is active for less than two cycles but not necessarily less than or equal to one cycle, which ultimately causes a read operation to bank (n) to occur.
Read V Self-Timed logic 2302 uses KRv(n) to generate a V read bank (n) pulse Rv(n) that is active for less than two cycles but not necessarily less than or equal to one cycle, which ultimately causes a read operation to bank (n) to occur.
Write U Self-Timed logic 2311 uses KW1u(n), along with Ru(n) and Wv(n) (to ensure that Wu(n) pulse begins after Ru(n) pulse or Wv(n) pulse ends), to generate a U write bank (n) pulse Wu(n) that is active for less than or equal to one cycle, which ultimately causes a write operation to bank (n) to occur. In other words, Wu(n) is a self-timed pulse derived from the logical function of “NOT(Ru(n)) AND NOT(Wv(n)) AND KW1u(n)”.
Write V Self-Timed logic 2312 uses KW1v(n), along with Rv(n) and Wu(n) (to ensure that Wv(n) pulse begins after Rv(n) pulse or Wu(n) pulse ends), to generate a V write bank (n) pulse Wv(n) that is active for less than or equal to one cycle, which ultimately causes a write operation to bank (n) to occur. In other words, Wv(n) is a self-timed pulse derived from the logical function of “NOT(Rv(n)) AND NOT(Wu(n)) AND KW1v(n)”.
The combined duration of Ru(n) active and Wu(n) active is less than or equal to two cycles. The combined duration of Rv(n) active and Wv(n) active is less than or equal to two cycles.
Register RAnu (2411) uses the rising edge of KRu(n) (see
Register RAnv (2413) uses the rising edge of KRv(n) (see
A Mux 2421 selects which of those bank (n) addresses, RAu(n) and/or WAu(n), or RAv(n) and/or WAv(n), are used to read and/or write to that particular memory bank. Ru(n) causes RAu(n) to be selected, Wu(n) causes WAu(n) to be selected, Rv(n) causes RAv(n) to be selected, and Wv(n) causes WAv(n) to be selected.
The output of DRA is A when AS is active, and is tri-stated when AS is inactive. The output of DRB is B when BS is active, and is tri-stated when BS is inactive. The output of DRC is C when CS is active, and is tri-stated when CS is inactive. The output of DRD is D when DS is active, and is tri-stated when DS is inactive. The output of DRX is 0 when AS, BS, CS, and DS are all inactive, and is tri-stated otherwise.
Mux DM 2621 time-multiplexes the captured beat one and beat two write data into a single write data stream Din that is bussed to each memory bank. K# clock “high” causes the beat one write data to be selected (i.e. muxed into the Din write data stream), and K clock “high” causes beat two write data to be selected (i.e. muxed into the Din write data stream). Like with Mux AM 2011 in
Note that the implementations of stages one and two in the write data paths allow for the KD clock edges to lead or trail the corresponding K clock edges by approximately a half cycle.
Register D0nua 2701 uses the rising edge of KWu(n) (see
D0n Mux 2721 selects which of those bank (n) beat one write data, D0u(n) or D0v(n), is used to write the particular memory bank. Wu(n) causes D0u(n) to be selected, and Wv(n) causes D0v(n) to be selected. D1n Mux 2722 selects which of those bank (n) beat two write data, D1u(n) or D1v(n), is used to write the particular memory bank. Wu(n) causes D1u(n) to be selected, and Wv(n) causes D1v(n) to be selected.
A and B are two inputs to the mux 2801, and Y is the output of the mux 2801. AS and BS are the two select signals that control whether Y is A or Y is B. Data Mux 2801 is the logical representation of the data mux. In some implementations, Data Mux 2801 comprises two drivers DRA 2811 and DRB 2812, and a Latch 2813. The output of DRA is A when AS is active, and is tri-stated when AS is inactive. The output of DRB is B when BS is active, and is tri-stated when BS is inactive. The Latch is used to keep output Y at its current state after both AS and BS are inactivated.
Note that when operating at maximum frequency (as illustrated in
Note also that when operating at maximum frequency and a read operation is initiated in cycle “n”, it must be to a different bank than the one read in cycle “n−1” because the two read operations will overlap some due to them being greater than one cycle in duration, and the one written in cycle “n−1” because the read operation will overlap with the entire write operation. These would be the only bank conflict restrictions in this particular implementation.
Note further that when operating at a slower frequency such that a read operation is less than one cycle in duration, a read operation initiated in cycle “n” can be to the same bank as the one read in cycle “n−1”, and in that case the only remaining bank conflict restriction is that the read in cycle “n” cannot be to the same bank as the one written in cycle “n−1”.
In addition to the above memory innovations and memory architecture, the present inventions also include, inter alia, methods of memory operation, methods of fabricating memory devices consistent with the features and/or functionality herein, products (such as SRAMs or products embodying SRAMs), and products produced via such processes. By way of example and not limitation, methods of memory fabrication herein may include known RAM manufacturing processes such as in CMOS technologies involving aspects such as p-mos and n-mos transistor formation, multiple metallization layers and/or local interconnects, among others. A variety of exemplary/staple processes here, for example, being set forth in the backgrounds/disclosures of U.S. Pat. Nos. 4,794,561, 5,624,863, 5,994,178, 6,001,674, 6,117,754, 6,127,706, 6,417,549, 6,894,356, and 7,910,427 as well as U.S. patent application publication No. US2007/0287239A1, which are incorporated herein by reference.
In some instances, aspects of the innovations herein may be achieved involving logic and/or logic instructions including program modules, executed in association with the circuitry, for example. In general, program modules may include routines, programs, objects, components, data structures, etc. that performs particular tasks or implement particular logic, control, delay or instructions. The inventions may also be practiced in the context of distributed circuit settings where circuitry is connected via communication buses, circuitry or links. In distributed settings, control/instructions may occur from both local and remote computing elements including memory storage devices.
As disclosed herein, features consistent with the present inventions may be utilized via and/or involved with computer hardware, software and/or firmware. For example, the systems and methods disclosed herein may be embodied in or used in connection with various forms including, for example, memory, data processors, such as in computing devices that also includes memory, a database, digital electronic circuitry, firmware, software, or in combinations of them. Further, while some of the disclosed implementations describe specific hardware components, systems and methods consistent with the innovations herein may be implemented in the context of any combination of hardware, software and/or firmware. Moreover, the above-noted features and other aspects and principles of the innovations herein may be implemented in various memory environments. Such environments and related applications may be specially constructed for performing the various routines, processes and/or operations according to the invention or they may include a general-purpose computer or computing platform selectively activated or reconfigured by code to provide the necessary functionality. The processes disclosed herein are not inherently related to any particular computer, network, architecture, environment, or other apparatus, and may be implemented by a suitable combination of hardware, software, and/or firmware. For example, various general-purpose machines may be used with programs written in accordance with teachings of the invention, or it may be more convenient to construct a specialized apparatus or system to perform the required methods and techniques.
Aspects of the method and system described herein, such as the logic, may be implemented as functionality programmed into any of a variety of circuitry, including programmable logic devices (“PLDs”), such as field programmable gate arrays (“FPGAs”), programmable array logic (“PAL”) devices, electrically programmable logic and memory devices and standard cell-based devices, as well as application specific integrated circuits. Some other possibilities for implementing aspects include: memory devices, microcontrollers with memory (such as EEPROM), embedded microprocessors, firmware, software, etc. Furthermore, aspects may be embodied in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. The underlying device technologies may be provided in a variety of component types, e.g., metal-oxide semiconductor field-effect transistor (“MOSFET”) technologies like complementary metal-oxide semiconductor (“CMOS”), bipolar technologies like emitter-coupled logic (“ECL”), polymer technologies (e.g., silicon-conjugated polymer and metal-conjugated polymer-metal structures), mixed analog and digital, and so on.
It should also be noted that the various logic, control and/or functions disclosed herein may be enabled using any number of combinations of hardware, firmware, and/or as data/instructions embodied in various machine-readable or computer-readable media, in terms of their behavioral, register transfer, logic component, and/or other characteristics. Computer-readable media in which such formatted data and/or instructions may be embodied include, but are not limited to, non-volatile storage media in various forms (e.g., optical, magnetic or semiconductor storage media), though does not include transitory media such as carrier waves.
Unless the context clearly requires otherwise, throughout the description and the elsewhere herein, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in a sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “hereunder,” “above,” “below,” and words of similar import refer to this application as a whole and not to any particular portions of this application. When the word “or” is used in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.
Although certain presently preferred implementations of the invention have been specifically described herein, it will be apparent to those skilled in the art to which the inventions pertain that variations and modifications of the various implementations shown and described herein may be made without departing from the spirit and scope of the innovations herein. Accordingly, it is intended that the inventions be limited only to the extent required by the applicable rules of law.
This application claims benefit/priority to U.S. provisional patent application Nos. 62/008,447, filed Jun. 5, 2014, and 62/008,449, filed Jun. 5, 2014, which are incorporated herein by reference in entirety.
| Number | Date | Country | |
|---|---|---|---|
| 62008447 | Jun 2014 | US | |
| 62008449 | Jun 2014 | US |
