The present invention relates to a method for forming a semiconductor device and a structure thereof; and, more particularly, to a T-gate forming method for a high electron mobility transistor and a gate structure thereof.
As well known, in high-speed components such as HEMTs (High Electron Mobility Transistors) which are used in satellite broadcasting receivers, high-speed logical circuits and power modules, a short gate length is required for a quick modulation while a large cross section of a pattern is also required in order to pass a high current therethrough.
From this, T-gates having a cross section of a ‘T’ shape are widely used in III-V compound semiconductor devices. The T-gate is formed of a gate head 102 and a gate foot 104 as shown in
To fabricate such T-gates with a gate foot width of 50 nm or below, an exposure process of the T-gate (i.e., electron beam lithography) and a process of stably forming the T-gate on a semiconductor substrate after depositing metals thereon are considerably important.
First, in the conventional exposure process of the T-gate having a gate foot width of 50 nm or below, the forward scattering and the gate head exposure have an effect on determining the gate foot definition. Here, increasing an accelerating voltage of an electron beam apparatus reduces the effect of the electron while decreasing sensitivity of the resist formed on the lowest layer reduces the effect of the gate head exposure. Further, the sensitivity of the resist can be reduced by developing it at a low temperature.
In order to fabricate the T-gate with a gate foot width of 50 nm or below by employing such an electron beam exposure process, the exposure process needs to be carried out by using an electron beam with an accelerating voltage of about 100 keV. Therefore, there are drawbacks in that its production cost is high and the semiconductor substrate can be damaged by the high accelerating voltage.
Next, the conventional T-gate having a straight gate foot is fabricated by decreasing the size of the gate foot to 50 nm or below in order to improve its characteristics, without decreasing the size of the gate head to prevent the increase of the gate resistance. However, since such size of the gate foot cannot support the gate head, the T-gate is not stably formed after depositing the metals and removing the resists, thereby resulting in a phenomenon where the T-gate falls to one side as shown in
If the T-gate formed in field effect transistors such as the HEMTs falls to one side, the schottky contact characteristics will be deteriorated, and thus, electrical characteristics of the semiconductor device will be degraded.
Accordingly, in the conventional forming process of the T-gate with a gate head having a wide width and a gate foot having a narrow width, the electron beam with a relatively high accelerating voltage is required to be used in the exposure process, and also a phenomenon that the T-gate falls to one side occurs due to the unstable structure of the T-gate. Therefore, there are problems in that the production cost is high and the characteristics of the semiconductor device are deteriorated.
It is, therefore, an object of the present invention to provide a T-gate forming method for high electron mobility transistors, wherein an exposure process is performed by using an electron beam with a relatively low accelerating voltage; and a gate structure thereof.
Another object of the present invention is to provide a T-gate forming method for high electron mobility transistors, wherein a gate foot of the gate has a transversal cross section of a bent shape to form a stable structure; and a gate structure thereof.
In accordance with one aspect of the present invention, there is provided a T-gate forming method for a high electron mobility transistor, the method including the steps of:
a first step of coating a first resist, a second resist and a third resist, each having an electron beam sensitivity different from each other, on a semiconductor substrate;
a second step of performing a first exposure process by using an electron beam on the semiconductor substrate where the first resist, the second resist and the third resist are coated and then selectively developing the third resist;
a third step of defining a gate head area by selectively developing the second resist to have a developed width wider than that of the third resist;
a fourth step of performing a second exposure process by using an electron beam on the semiconductor substrate where the third resist and the second resist are selectively developed and then selectively developing the first resist in a bent shape at a temperature lower than in the development of the second and the third steps; and
a fifth step of depositing metallic materials on the first resist, the second resist and the third resist which are selectively developed and then removing the first resist, the second resist and the third resist to form a T-gate with the gate head and a gate foot.
In accordance with another aspect of the present invention, there is provided a gate structure of a high electron mobility transistor, the gate structure including:
a gate foot formed on a semiconductor substrate; and
a gate head, with a width wider than the gate foot, formed on the gate foot,
wherein a transversal cross section of the gate foot is of a bent shape.
The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which:
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that they can be readily implemented by those skilled in the art.
Referring to 2A, a first resist 202, a second resist 204 and a third resist 206 are sequentially coated on a semiconductor substrate 200. For example, a PMMA (Polymethyle Methacrylate) resist is coated in a thickness from 90 nm to 110 nm as the first resist 202, and a PMGI (Poly-Dmethylgutarimide) resist is then coated in a thickness from 450 nm to 550 nm as the second resist 204, and finally a PMMA-MAA (Polymethyle Methacrylate-Methyle Methacrylate) resist is coated in a thickness from 180 nm to 220 nm as the third resist 206. Further, the first resist 202, the second resist 204 and the third resist 206 can be coated, for example, by a spin-coating technique. Hereinafter, such layered structure of the first, the second, and the third resist 202, 204 and 206 will be simply referred to as a “structure”.
After coating each resist, baking is performed thereto for about 5 minutes at a temperature from 180° C. to 200° C. After this, the structure is cooled by the air for about 10 minutes, and then a first exposure process is carried out. For example, the first exposure process is performed at an energy level of 90 μC/cm2 to 100 μC/cm2. After finishing the exposure process, the third resist 206 of the PMMA-MAA resist formed on the top of the structure is selectively developed at room temperature by using a developing solution with a ratio of MIBK:IPA being 1:3, as shown in
Next, on the semiconductor substrate 200 where the third resist 206 is selectively removed, the second resist 204 of the PMGI resist formed at the middle layer is selectively developed at room temperature by using a developing solution such as a PMGI-101 to define an area where a gate head will be formed, as shown in
Thereafter, a second exposure process is performed on the semiconductor substrate 200 where the second resist 204 is selectively removed. The second exposure process is performed, for example, at an energy level of 1000 μC/cm2 to 4000 μC/cm2, on a part of the first resist 202 over which the central portion of the area formed by selectively removing the second resist 204 to form the gate head is located. After that, as shown in
Through these processes, the electron beam is irradiated to the first resist 202 of the PMMA resist (the bottom layer of the structure) which remains after developing the gate head part, so the forward scattering due to the resist can be reduced. Further, the effect of the first exposure process can be decreased because the sensitivity of the first resist 202 of the PMMA resist formed at the lowest layer of the structure is reduced due to a low temperature development.
Subsequently, as shown in
Finally, the first resist 202, the second resist 204 and the third resist 206, in which the T-gate 208 is formed, remaining on the semiconductor substrate 200 are removed by an asking process using Ar and O2 to form the T-gate 208 on the semiconductor substrate 200, as shown in
Accordingly, in a process of forming transistors of semiconductor devices, T-gates having a relatively wide gate head and a relatively narrow gate foot can be formed through the first and the second exposure process by using the electron beam.
As a result of such comparison, in case of the room temperature development shown in
On the other hand, in case of the low temperature development as shown in
Accordingly, the finer gate can be formed by developing at a low temperature after performing the first and the second exposure processes which use the electron beam.
Referring to
Further,
Especially, as can be seen by comparing the T-gate having the conventional straight gate foot and the T-gate having the bent gate foot in accordance with the present invention by referring to
After that, the T-gate is formed on the semiconductor substrate where both the source region and the drain region are formed by using the electron beam in accordance with the present invention, and then a gate recess is performed by using an etching solution based on citric acids.
Further,
On the other hand,
Therefore, if high electron mobility transistors including a T-gate with a bent gate foot are fabricated through the first and the second exposure processes by using the electron beam in accordance with the present invention, transistors with a T-gate having a size of tens of nanometers can be stably formed.
In accordance with the present invention, a first, a second and a third resist are coated on a semiconductor substrate, wherein each resist has an electron beam sensitivity different from each other. On the semiconductor substrate where the first, the second and the third resist are coated, a first exposure process using an electron beam is performed, and then the third resist is selectively developed. Thereafter, the second resist is selectively developed to have a developed width wider than that of the third resist in order to define a gate head area. On the semiconductor substrate where the third and the second resist are selectively developed, a second exposure process is performed by using an electron beam, and then the first resist is selectively developed in a bent shape at a temperature lower than in the development of the second and the third resist. Finally, after depositing metallic materials on the first, the second and the third resist which are selectively developed, the first, the second and the third resist are removed to form a T-gate with the gate head and a gate foot. Accordingly, by means of performing the first and the second exposure process by using an electron beam and developing each of the resists by using a developing solution different from each other at a temperature different from each other, a stable T-gate with a bent-shaped gate foot can be fabricated.
While the invention has been shown and described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.
Number | Date | Country | Kind |
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10-2006-0108497 | Nov 2006 | KR | national |
This application is a divisional of co-pending U.S. application Ser. No. 11/700,946, filed on Feb. 1, 2007, which claims priority to Korean Patent Application No. 10-2006-0108497, filed on Nov. 3, 2006. The entire disclosure of co-pending U.S. application Ser. No. 11/700,946 and Korean Patent Application No. 10-2006-0108497 are herein incorporated by reference in their entirety.
Number | Date | Country | |
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Parent | 11700946 | Feb 2007 | US |
Child | 13051277 | US |