Claims
- 1. A thin film transistor made by:
- providing a substrate including a dielectric layer in contact with a pattern photoresist layer;
- etching the exposed dielectric layer with a gas comprising SF.sub.6 and Cl.sub.2 to form at least one etched opening; and,
- depositing a conductive material into at least a portion of the opening.
- 2. The thin film transistor of claim 1, wherein said substrate includes substantially SiO.sub.2 and BaO.
- 3. The thin film transistor of claim 1, wherein said substrate is made of glass.
- 4. The thin film transistor of claim 1, wherein said dielectric layer includes silicon nitride or silicon oxide.
- 5. The thin film transistor of claim 1, wherein said conductive material includes a material selected from the group consisting of indium-tin-oxide, aluminum, tantalum and molybdenum.
- 6. The thin film transistor of claim 1, wherein said at least one etched opening has sidewalls sloped at a taper of between about 20.degree. and about 85.degree. as measured from a top surface of the substrate.
- 7. The thin film transistor of claim 1, wherein said at least one etched opening has sidewalls sloped at a taper of between about 35.degree. and about 70.degree. as measured from a top surface of the substrate.
- 8. A thin film transistor made by:
- providing a substrate including a dielectric layer in contact with a pattern photoresist layer;
- etching the exposed dielectric layer and the pattern photoresist layer with a gas comprising Cl.sub.2 and SF.sub.6 in a ratio of about 0.5-1.5 and at a pressure of about 5-100 mTorr to form at least one etched opening, and
- depositing a conductive material in at least a portion of the at least one etched opening.
- 9. The thin film transistor of claim 8, wherein the pressure is about 20-50 mTorr, and wherein the at least one etched opening has sloped sidewalls substantially free of an undercut in the dielectric layer.
- 10. The thin film transistor of claim 8, wherein the ratio of Cl.sub.2 and SF.sub.6 is about 1.
- 11. The thin film transistor of claim 9, wherein said sloped sidewalls have a taper of at least 20.degree. as measured from a top surface of said substrate.
- 12. A thin film transistor made by:
- providing a substrate including an insulative material,
- depositing about 100-300 nanometers of a dielectric layer comprising silicon nitride on the substrate,
- depositing and patterning a photoresist layer on said dielectric material,
- etching the dielectric and photoresist layers with a mixture of SF.sub.6 gas and Cl.sub.2 gas in a ratio of Cl.sub.2 to SF.sub.6 in the range of about 0.5 to 1.5; and,
- producing at least one opening having substantially sloped sidewalls
- wherein the sloped sidewalls are substantially free of undercutting.
- 13. The thin film transistor of claim 12, wherein the SF.sub.6 has a flowrate of about 200 sccm and the Cl.sub.2 has a flowrate of about 200 sccm.
- 14. The thin film transistor of claim 13, wherein the gas mixture further includes O.sub.2 at a flowrate of about 100 sccm.
- 15. The thin film transistor of claim 14, wherein the gas mixture further includes a carrier effective flowrate of a member selected from the group consisting of argon, helium and mixtures thereof.
- 16. The thin film transistor of claim 12, wherein the photoresist layer has a thickness of about 1200 nanometer.
- 17. The thin film transistor of claim 12, wherein the etching occurs at power density of about 0.4-2 watts/centimeter.sup.2.
Parent Case Info
This is a divisional of application Ser. No. 08,541,066, filed Oct. 11, 1995, now U.S. Pat. No. 5,728,608.
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Divisions (1)
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Number |
Date |
Country |
Parent |
541066 |
Oct 1995 |
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