Patent Application
20250078916
The present disclosure generally relates to memory processing, and more particularly, to a memory compiler identifying breakpoints for a memory.
Memory plays an important role in electronic devices such as smartphones and computers. A memory compiler may be used to efficiently integrate memory into electronic devices. Memory compilers simplify the process of designing and improving memory structures. A memory compiler may be used to automate the generation of memory arrays based on predefined specifications. Based on user specifications, a memory compiler may provide memory architectures that can be implemented on a chip.
The following presents a simplified summary of one or more aspects of the present disclosure, in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.
Certain aspects of the present disclosure include a method for memory processing. The method generally includes determining, via one or more processors and for each of different quantities of columns per section of a memory, a read signal indicating a change in a bitline signal during a read window based on at least one calculated slope of the bitline signal during the read window, where the read signal being determined for each of the different quantities of the columns per section of the memory yields a plurality of read signals; determining a difference between at least two of the plurality of read signals, identifying breakpoints within the memory based on the difference between the at least two of the plurality of read signals. The method also includes generating a representation of the memory based on the breakpoints.
Certain aspects of the present disclosure include an apparatus for memory processing. The apparatus generally includes a storage device. The apparatus also includes one or more processors coupled to the storage device, the one or more processing being configured to: determine, for each of different quantities of columns per section of a memory, a read signal indicating a change in a bitline signal during a read window based on at least one calculated slope of the bitline signal during the read window, where the read signal being determined for each of the different quantities of the columns per section of the memory yields a plurality of read signals; determine a difference between at least two of the plurality of read signals; identify breakpoints within the memory based on the difference between the at least two of the plurality of read signals; and generate the representation of the memory based on the breakpoints.
Certain aspects of the present disclosure include a non-transitory computer-readable medium having instructions stored thereon, that when executed by one or more processors, cause the one or more processors to: determine, for each of different quantities of columns per section of a memory, a read signal indicating a change in a bitline signal during a read window based on at least one calculated slope of the bitline signal during the read window, wherein the read signal being determined for each of the different quantities of the columns per section of the memory yields a plurality of read signals; determine a difference between at least two of the plurality of read signals; identify breakpoints within the memory based on the difference between the at least two of the plurality of read signals; and generate the representation of the memory based on the breakpoints.
The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale.
Certain aspects of the present disclosure are directed towards a memory compiler used to generate a representation of memory. The memory may include an array of memory cells, such as static random access memory (SRAM) memory cells, as described in more detail herein. The memory compiler may calculate read signals for different numbers of columns per section of memory. Based on the read signals, the compiler may identify breakpoints for the memory. The compiler may perform resistance and capacitance matching of different global lines of the memory to reduce the number of breakpoints. The compiler may use the breakpoints to tune the memory (e.g., tune read and write margins for the memory). Performing the tuning of the memory may involve various simulations for different sections of the memory based on the breakpoints. Thus, reducing the number of breakpoints results in a reduction in the simulation overhead of the compiler when tuning the memory.
Advantages of the present disclosure include, but are not limited to, increased efficiency associated with generating a memory representation by a memory compiler. Thus, certain aspects provide quicker memory design closure (e.g., memory characterization and tuning), reduced machine resources associated with the memory compiler, and improved memory designs (e.g., by allowing for a more effective tuning of the read and write margins of the memory).
The size of any memory is represented by the multiplication of rows and columns, where rows represent the number of WLs and columns represent the number of BLs. The access time and cycle time in embedded memories vary across the rows and columns. The change in rows and columns of memory may be tracked to automatically adjust the self-time associated with the memory. A circuit for adjusting the self-time may be referred to as a self-time circuit, which sometimes includes resistance and capacitance tracking, logical delays, and pull-down circuits. Self-time generally refers to identifying a delay associated with performing certain operations, such as a read or write operation, for the memory. For example, a self-time signal (e.g., having a certain self-time pulse width) may be generated to control the read operations of the memory based on the calculated self-time parameters. It is important to reduce such self-time delays to provide faster operations for the memory. The number of simulations increases for every major activity of memory development, like self-time tuning, margin closure, and characterization.
Creating an embedded memory compiler is a task that involves both design (self-time tuning) and computing resources (simulations). With the addition of column multiplexing, multi-bank memory, and many other options for memory compilers to implement, a memory compiler may have to run many simulations to improve (e.g., optimize) the self-time loop.
Achieving self-time tuning for the compiler range involves performing many simulations and precise design tuning like resistance and capacitance (RC) tuning or delay tuning. Self-time tuning parameters (e.g., a read signal, also referred to herein as a minimum read signal) may be determined in certain aspects of the present disclosure. Deviation of the self-time tuning parameters across rows and columns of the memory may be observed to determine design breakpoints for the compiler, as described in more detail herein. For example, a number of design breakpoints may be reduced by reducing a mismatch between resistance and capacitance values associated with different signals involved in self-time tuning, as described in more detail herein.
A user may select various features to be implemented for the memory system 100. For example, as shown in
In some aspects, a large memory array may be divided into different sections based on identified breakpoints. For instance, assume a memory with 256 rows and 256 columns. The memory's access and cycle times change across the columns and rows. So to efficiently tune the memory array, the array may be divided into multiple sections. For instance, the memory array may be divided into multiple sections having 32 rows and 32 columns. Each of the sections may be tuned separately. The point of division of the memory array into respective sections may be referred to as a breakpoint. Reducing the number of breakpoints (e.g., memory array sections) results in a reduced number of simulations that would have to be performed by the compiler to tune the memory array. In some aspects of the present disclosure, the memory compiler may determine self-timing parameters and provide breakpoints to increase tuning efficiency.
where Iread is the bitcell read current (e.g., the current consumption of a bitcell during read operations), Vdd is the supply voltage for the bit cell, Vth is the device threshold voltage (e.g., threshold voltage associated with pass-gate transistors 102, 118), Cht@array is the bitline capacitance for the array memory cell, Cbt@io is the bitline capacitance in IO (e.g., the capacitance associated with the IO interface for the bitline), Rows is the total number of wordlines of the memory, Vwl_target is the wordline voltage level target (e.g., a logic high voltage at the WL), and EW is the effective read window. The effective read window may refer to a duration of time from when a WL signal reaches 80% of a logic high voltage until a sense enable signal reaches 50% of the logic high voltage, as described in more detail herein. Thus, the minimum read signal may correspond to a signal generated at a BLB (or BL) (e.g., a change in voltage at the BLB) during the effective read window.
In some cases, the effective read window may be split into two sections, including a first time duration (labeled “t1”) from when the WL signal 402 reaches 80% of the logic high voltage till the WL signal 402 reaches 98% of the logic high voltage, and a second time duration (labeled “t2”) from when WL signal 402 reaches 98% of the logic high voltage until the SAEB signal 408 reaches 50% of the logic high voltage, as shown. In certain aspects of the present disclosure, the read signal may be calculated based on a calculated slope of the BLB signal 406 during the first time duration and a calculated slope of the BLB signal 406 during the second time duration, providing a more accurate read signal calculation. The read signal may be calculated for different quantities of columns per section (CPS) of the memory array. In other words, different sections of memory may be considered with different numbers of columns. For example, the read signal may be calculated for 32 columns per section of memory, 48 columns per section of memory, and so on, as described in more detail herein. In calculating the slope of the read signal (BLB signal 406), the entire capacitance from a top memory bank row to the sense amplifier internal nets may be considered. The read signal may be calculated using the expression provided herein and used to calculate deviation across different CPS of the memory array to determine design breakpoints. For instance, referring back to
Referring back to
Referring back to
At block 602, the compiler may determine, for each of different quantities of columns per section of the memory (e.g., for the different CPS shown in
In some aspects, the read window may include a time duration from a rising edge of a wordline signal (e.g., WL signal 402) of the memory until a rising edge of a sense amplifier enable signal (e.g., SAEB signal 408) of the memory. The rising edge of the wordline signal may include a time at which the wordline signal reaches 80% of a logic high voltage, and the rising edge of the sense amplifier enable may include a time at which the sense amplifier enable signal reaches 50% of the logic high voltage.
In some aspects, the at least one calculated slope may include a first calculated slope of the bitline signal for a first portion (e.g., time duration t1 shown in
At block 604, the compiler may determine a difference between at least two of the plurality of read signals. For example, the at least two of the plurality of read signals may be for two consecutive quantities of the columns per section of the memory (e.g., for CPS 32 and 48, as described with respect to
At block 606, the compiler identifies breakpoints within the memory based on the difference between the at least two of the plurality of read signals, and at block 608, generates the representation of the memory based on the breakpoints. For example, generating the representation of the memory based on the breakpoints may include separately tuning different sections of the memory based on the breakpoints within the memory. In some aspects, the compiler may reduce a resistance or capacitance mismatch between at least two lines (e.g., a wordline and a sense amplifier enable line) of the memory prior to determining the plurality of read signals
In some aspects, the at least one calculated slope may be calculated based on at least one of a read current (e.g., Iread) associated with a bitcell of the memory, a supply voltage (e.g., Vdd) for the memory, a threshold voltage (e.g., Vth) of the memory, a bitline capacitance (e.g., Cbt@array) associated with the memory, a capacitance (e.g., Cbt@io) at a bitline input and output (I/O) interface for the memory, a quantity of wordlines (e.g., Rows) of the memory, or a wordline voltage level target (e.g., Vwl_target) of the memory.
The compiler described herein may determine memory self-time breakpoints using pre-simulation techniques. For example, resistance, capacitance, or bitcell parameters such as read current and write time may be used to calculate read signals to determine the breakpoints, as described. Certain aspects of the present disclosure reduce the simulation overhead of the compiler and provide design features early in the development phase, reducing repetitions associated with self-time loop closure and improving productivity.
Certain aspects provide quicker design closure and productivity improvements. The techniques described herein are used to identify design breakpoints and resistance and capacitance specifications before a design tuning cycle using extracted netlists, reducing iterations for self-time closure. For example, certain aspects improve productivity by reducing a number of breakpoints compared to conventional compilers. Machine resource usage may be reduced by reducing the number of design breakpoints. Reducing the number of breakpoints allows for tuning of the read and write margins of the memory more efficiently. Reduction in design breakpoints also reduces the trend mismatch across rows and columns. A re-buffer breakpoint may be identified based on RC specifications, in some aspects.
Specifications for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. A high-level representation may be used to design circuits and systems, using a hardware description language (‘HDL’) such as VHDL, Verilog, System Verilog, SystemC, MyHDL or OpenVera. The HDL description can be transformed to a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description. Each lower representation level that is a more detailed description adds more useful detail into the design description, for example, more details for the modules that include the description. The lower levels of representation that are more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of representation language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each level of representation are enabled for use by the corresponding tools of that layer (e.g., a formal verification tool). A design process may use a sequence depicted in
During system design 714, functionality of an integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or lines of code), and reduction of costs, etc. Partitioning of the design into different types of modules or components can occur at this stage.
During logic design and functional verification 716, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, the components of the circuit may be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification.
During synthesis and design for test 718, HDL code is transformed to a netlist. In some embodiments, a netlist may be a graph structure where edges of the graph structure represent components of a circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to the specified design. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify that the integrated circuit satisfies the requirements of the specification.
During netlist verification 720, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.
During layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the circuit components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions can be performed. As used herein, the term ‘cell’ may specify a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flipflop or latch). As used herein, a circuit ‘block’ may refer to two or more cells. Both a cell and a circuit block can be referred to as a module or component and are enabled as both physical structures and in simulations. Parameters are specified for selected cells (based on ‘standard cells’) such as size and made accessible in a database for use by EDA products.
During analysis and extraction 726, the circuit function is verified at the layout level, which permits refinement of the layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDL design specification. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.
During tape-out, data is created to be used (after lithographic enhancements are applied if appropriate) for production of lithography masks. During mask data preparation 732, the ‘tape-out’ data is used to produce lithography masks that are used to produce finished integrated circuits.
A storage subsystem of a computer system (such as computer system 800 of
The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.
The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 818, which communicate with each other via a bus 830.
Processing device 802 represents one or more processors such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 802 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 802 may be configured to execute instructions 826 for performing the operations and steps described herein.
The computer system 800 may further include a network interface device 808 to communicate over the network 820. The computer system 800 also may include a video display unit 810 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 812 (e.g., a keyboard), a cursor control device 814 (e.g., a mouse), a graphics processing unit 822, a signal generation device 816 (e.g., a speaker), graphics processing unit 822, video processing unit 828, and audio processing unit 832.
The data storage device 818 may include a machine-readable storage medium 824 (also known as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and/or within the processing device 802 during execution thereof by the computer system 800, the main memory 804 and the processing device 802 also constituting machine-readable storage media.
In some implementations, the instructions 826 include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium 824 is shown in an example implementation to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device 802 to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.
In some aspects of the present disclosure, the processing device 802 may include a memory compiler 827. The memory compiler 827 may generate a representation of a memory in accordance with certain aspects of the present disclosure.
Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.
The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.
The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.
The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.
In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular tense, more than one element can be depicted in the figures and like elements are labeled with like numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.
