Teradyne J971 Spectrum Architecture, Teradyne, Inc. |
Teradyne J971 System Description, Teradyne, Inc., pp. 1-21 (May 1991). |
Teradyne J971 Preliminary Specification (100 MHz Version), Teradyne, Inc. pp. 1-15 (Jun. 25, 1991). |
D. F. Murray and C. M. Nash, Critical Parameters for High-Performance Dynamic Response Measurements, Semiconductor Test Systems Division (STS), Tektronix, Inc., pp. 462-471 (IEEE 1990). |
H. Vitale, High Speed CMOS Reflection Reduction, Trillium Engineering, Trillium Applications Note No. APN 028 (Aug. 1988). |
H. Vitale, Use of the Programmable Load to Reduce Reflections in Test Applications of High Speed CMOS, Trillium Test Systems Applications Note (Oct. 1987). |
Motorola High-Speed CMOS Integrated Circuits, Motorola, Inc. pp. 4--4 (1983). |
Fairchild Advanced CMOS Technology Logic Data Book, Fairchild Semiconductor Corp., pp. 2-3 to 2-7 (1987). |
MECL System Design Handbook, Motorola, Inc., pp. 77-81 (1983). |
J. Millman, Microelectronics-Digital and Analog Circuits and Systems, pp. 338-343 (1979). |
Product Description, Rev. 2, pp. 33-34 (May 1986). |
M. Ferland, Device Output Loading, IEEE, pp. 130-132 (1978). |
MegaOne VLSI Test System, Megatest Corp., 3 pages (1983). |
J967 VLSI Test System, Teradyne, Inc. p. 25 (May, 1985). |