Claims
- 1. A drive circuit for an automatic test equipment formatter, the drive circuit comprising:
an event logic section comprising a plurality of event logic interfaces, each event logic interface capable of decoding signals received from an external event timing generation circuit; a linear delay element section comprising a plurality of linear delay elements, each linear delay element being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from an event logic interface; and drive logic programmable to operate in any of a plurality of modes, each mode providing a different combination of drive signals or timing markers or both.
- 2. The drive circuit of claim 1 wherein the drive circuit further is programmable to provide the combination of drive signals or timing markers at different frequencies.
- 3. The drive circuit of claim 1 wherein each event logic interface is paired with a corresponding linear delay element to form a channel to provide signals to the drive logic.
- 4. The drive circuit of claim 3 wherein the drive circuit is configurable to route signals defining a drive signal or timing marker through a plurality of channels in parallel.
- 5. The drive circuit of claim 1 further comprising a register section being configured to receive control setup information from an external source.
- 6. The drive circuit of claim 5 further comprising a timing measurement unit section, said timing measurement unit section further comprising at least two timing measurement unit multiplexers.
- 7. The drive circuit of claim 1 wherein the drive logic comprises a plurality of programmable multiplexers.
- 8. The drive circuit of claim 7 wherein the plurality of multiplexers are programmable to logically combine signals received from a plurality of linear delay elements to form a desired combination of drive signals or timing markers or both.
- 9. The drive circuit of claim 7 further comprising a plurality of logic elements configurable to logically combine signals received from one or more multiplexers.
- 10. The drive circuit of claim 1 wherein each event logic interface is paired with a corresponding linear delay element to form a channel to provide signals to the drive logic, and wherein a first mode uses a different number of channels than a second mode.
- 11. The drive circuit of claim 10 wherein the different number of channels corresponds to a number of device pins to be driven.
- 12. The drive circuit of claim 1 wherein the drive logic further is configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals.
- 13. The drive circuit of claim 12 wherein each event logic interface is paired with a corresponding linear delay element to form a channel to provide signals to the drive logic, and wherein each strobe mode uses a different number of channels to form corresponding strobe signals.
- 14. A response circuit for an automatic test equipment formatter, the response circuit comprising:
an event logic section comprising a plurality of event logic interfaces, each event logic interface capable of decoding signals received from an external event timing generation circuit; a linear delay element section comprising a plurality of linear delay elements, each linear delay element being coupled to a corresponding event logic interface and being capable of generating timing markers corresponding to signals received from an event logic interface; and response logic programmable to operate in any of a plurality of modes, each mode providing a different combination of strobe signals.
- 15. The response circuit of claim 14 wherein the response circuit further is programmable to receive response signals from one or more pin-electronics comparators.
- 16. The response circuit of claim 14 wherein each event logic interface is paired with a corresponding linear delay element to form a channel to provide signals to the response logic.
- 17. The response circuit of claim 16 wherein the response circuit is configurable to route response signals received from one or more pin-electronics comparators to a plurality of channels in parallel.
- 18. The response circuit of claim 14 further comprising a register section being configured to receive control setup information from an external source.
- 19. The response circuit of claim 18 further comprising a timing measurement unit section, said timing measurement unit section further comprising at least two timing measurement unit multiplexers.
- 20. The response circuit of claim 14 wherein the response logic comprises a plurality of programmable multiplexers.
- 21. The response circuit of claim 20 wherein the plurality of multiplexers are selectively programmable to cause the response logic to operate in any of the plurality of different modes, each mode corresponding to a different number of pin-electronics comparators from which response signals are to be received.
- 22. The response circuit of claim 21 wherein each event logic interface is paired with a corresponding linear delay element to form a channel to receive response signals from the response logic, and wherein a first mode uses a different number of channels than a second mode.
- 23. The response circuit of claim 22 wherein the response circuit is configured in the first mode to receive response signals from a single pin-electronics comparator and to use four merged channels to generate fail outputs.
- 24. The response circuit of claim 22 wherein the response circuit is configured in the second mode to receive response signals from two separate pin-electronics comparators and to use two merged channels for each pin-electronics comparator to generate fail outputs.
- 25. The response circuit of claim 21 wherein each event logic interface is paired with a corresponding linear delay element to form a channel to receive response signals from the response logic, and wherein the response circuit is configured in a third mode to receive response signals from four pin-electronics comparators and to use a separate channel for each pin comparator to generate fail outputs.
- 26. A test system formatter comprising:
a programmable drive circuit configurable to operate in any of a plurality of drive modes, each mode providing a different combination of drive signals or drive timing markers or both; and a programmable response circuit configurable to operate in any of a plurality of strobe modes, each strobe mode corresponding to a different combination of strobe signals.
- 27. The formatter of claim 26 further comprising a plurality of drive channels, each drive channel for providing signals to the drive circuit to be used to generate drive signals or drive timing markers or both.
- 28. The formatter of claim 27 wherein each drive channel comprises an event logic interface and a corresponding linear delay element.
- 29. The formatter of claim 27 wherein the programmable drive circuit is configurable to route signals through a plurality of channels in parallel to be used for generating drive signals or timing markers or both.
- 30. The formatter of claim 26 further comprising a plurality of response channels, each response channel for receiving response signals from one or more pin-electronics comparators.
- 31. The formatter of claim 30 wherein each response channel comprises an event logic interface and a corresponding linear delay element.
- 32. The formatter of claim 30 wherein the programmable response circuit is configurable to route response signals through a plurality of response channels in parallel to be used to generate fail signals.
- 33. A method of configuring a integrated circuit test system, the method comprising:
providing a test system having a formatter with a programmable drive circuit; configuring the test system to be in communication with a device under test; and programming the drive circuit to operate in a selected mode from among a plurality of modes, each mode defining a different combination of formatted drive signals or drive signal timing markers or both.
- 34. The method of claim 33 further comprising programming the drive circuit to receive input signals from a plurality of channels in parallel.
- 35. The method of claim 34 wherein input signals from a plurality of channels are merged to generate one or more drive signals.
- 36. The method of claim 35 wherein merging input signals from a plurality of channels increases a drive signal data rate.
- 37. The method of claim 35 further comprising:
providing a programmable response circuit; and programming the response circuit to operate in a selected mode from among a plurality of modes, each mode corresponding to a different number of pin-electronics comparators from which response signals are to be received.
RELATED APPLICATION
[0001] This application claims priority to U.S. Provisional Patent Application No. 60/277,185, filed Mar. 19, 2001.
Provisional Applications (1)
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Number |
Date |
Country |
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60277185 |
Mar 2001 |
US |