Patent Application
20140244203
1. Technical Field
The disclosure generally relates to testing systems and methods, and particularly to a testing system and method for an inter-integrated circuit bus (I2C).
2. Description of Related Art
I2C buses are widely used for serial data communication between multiple devices. Real-time signals transmitted by the I2C bus are manually tested by using an oscillograph. However, manually testing the I2C bus using the oscillograph may not be accurate or efficient.
Therefore, there is room for improvement within the art.
Many aspects of the embodiments can be better understood with reference to the following drawings. The components in the drawings are not necessarily drawn to scale, the emphasis instead being placed upon clearly illustrating the principles of the embodiments. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the views.
The disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, in which like reference numerals indicate similar elements. It should be noted that references to “an” or “one” embodiment in this disclosure are not necessarily to the same embodiment, and such references can mean “at least one.”
In general, the word “module,” as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a programming language such as Java, C, or assembly. One or more software instructions in the modules may be embedded in firmware, such as in an erasable-programmable read-only memory (EPROM). The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of non-transitory computer-readable medium or other storage device. Some non-limiting examples of non-transitory computer-readable media are compact discs (CDs), digital versatile discs (DVDs), Blu-Ray discs, Flash memory, and hard disk drives.
The tested motherboard 300 includes an I2C master control device 310 and an I2C slave device 320 connected to the I2C master device 310 by the I2C bus. The I2C bus includes a Serial Data (SDA) line 330 and a Serial Clock (SCL) line 340. In one embodiment, the I2C master control device 310 is a central processing unit (CPU), and the I2C slave device is a register. The oscillograph 200 detects real-time signals of the SDA line 330 and the SCL line 340.
The testing device 100 includes a master control module 10, a setting module 20, a data read module 30, a data converting module 40, a data determining module 50, a testing report generating module 60, and a display module 70.
The master control module 10 sends a testing command to the I2C master control device 310 to turn on the tested motherboard 300, so that the I2C master control device 310 can send the real-time signals to the I2C slave device 320 through the SDA line 330 and the SCL line 340. The setting module 20 sets predetermined parameters, such as a unit voltage value, an original position, and a trigger condition, of the oscillograph 200. The oscillograph 200 collects the real-time signals of the I2C bus. The data read module 30 reads the real-time signals collected by the oscillograph 200. The data converting module 40 converts the real-time signals into accessible data, such as binary code. The data determining module 50 determines whether the accessible data complies with the predetermined parameters. The testing report generating module 60 generates a testing report depicting whether the accessible data complies with the predetermined parameters. The display module 70 displays the testing report on a display device (not shown).
In step S1, the master control module 10 sends a testing command to the I2C master control device 310 to start the I2C master control device 310.
In step S2, the I2C master control device 310 sends the real-time signals to the I2C slave device 320. The real-time signals include serial data and clock data.
In step S3, the setting module 20 sets predetermined parameters of the oscillograph 200.
In step S4, the oscillograph 200 collects the real-time signals of the I2C bus.
In step S5, the data read module 30 reads the real-time signals.
In step S6, the data converting module 40 converts the real-time signals into accessible data, such as binary code.
In step S7, the data determining module 50 determines whether the accessible data complies with the predetermined parameters.
In step S8, the testing report generating module 60 generates a testing report depicting whether the accessible data complies with predetermined parameters.
In step S9, the display module 70 displays the testing report on a display device.
Although numerous characteristics and advantages have been set forth in the foregoing description of embodiments, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in the matters of arrangement of parts within the principles of the disclosure to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.
In particular, depending on the embodiment, certain steps or methods described may be removed, others may be added, and the sequence of steps may be altered. The description and the claims drawn for or in relation to a method may give some indication in reference to certain steps. However, any indication given is only to be viewed for identification purposes, and is not necessarily a suggestion as to an order for the steps.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2013100618584 | Feb 2013 | CN | national |
