Patent Application
20220390694
Embodiments of the present description generally relate to the field of integrated circuit assemblies and, more particularly, to the integration of thermal interface structures for the removal of heat from optical communication devices.
The integrated circuit industry is continually striving to produce ever faster and smaller integrated circuit devices for use in various server and mobile electronic products, including, but not limited to, computer server products and portable products, such as wearable integrated circuit systems, portable computers, electronic tablets, cellular phones, digital cameras, and the like.
As these goals are achieved, the integrated circuit devices become smaller. However, communication demands have been increasing considerably faster than scaling (e.g., Moore's law) can achieve. For example, machine intelligence systems are requiring core counts in the thousands, “near compute” memory of greater than 10 gigabytes, connectivity bandwidth of greater than one terabyte per second between multiple nodes, low latency, thermal control, and good manufacturability, as will be understood to those skilled in the art. Of course, signal loss significantly increases with metal conductive routes (used for electrical interconnects) as signaling frequency increases and distance between the integrated circuit devices increases. Furthermore, the routing of the conductive routes becomes increasingly complex as more integrated circuit devices are added to an integrated circuit package. Thus, optical interconnects are being used to replace electrical interconnects, as optical interconnects offer very high bandwidths compared to electrical interconnects. As will be understood to those skilled in the art, photonic integrated circuit devices are used to convert electrical signals to optical signals. As will be further understood, photonic integrated circuit devices may have lasing components, amplifiers, and/or other electrical circuits which generate significant power densities (e.g., about 50 to 150 watts per square millimeter compared to a processing or computing device which may have power densities of about 5 to 50 watts per square millimeter, depending on use condition). Furthermore, optical components, such as lasers, can typically only tolerate a maximum temperature of between about 70 and 90 degrees Celsius compared to the maximum junction temperatures on processing or computing devices of between about 100 to 110 degrees Celsius.
Ordinarily, heat is removed with a heat dissipation device, such as an integrated heat spreader, a heat sink, a heat pipe, a thermoelectric cooler, a cold plate, and the like, thermally attached with thermal interface materials to the integrated circuit devices within the integrated circuit package. With “non-photonic” integrated circuit devices, the thermal interface materials may be greases, gels, pads, films, and the like, with a high loading of thermally conductive filler materials, such as metal and/or ceramic particles. However, such thermal interface materials may not be compatible with photonic integrated circuit devices. For example, with silicon photonic integrated circuit devices, particularly those with thin buried oxide layers, the silicon substrate, from which the device is made, must be thinned in order to remove silicon in areas where optical waveguides are located to ensure that the optical beam stays in the waveguide and does not couple with the silicon substrate, as will be understood to those skilled in the art. As previously discussed, the silicon photonic integrated circuit devices need to be thermally coupled to the heat dissipation device in order to maintain an acceptable operating temperature. The required thinning of the silicon photonic integrated circuit devices will bring the thermal interface materials into close proximity with the waveguides of the silicon photonic integrated circuit devices. However, the thermally conductive fillers in the thermal interface materials will absorb, scatter, and/or couple the light from the waveguides, resulting in significant waveguide insertion loss and sometimes even “optical blindness” where no light comes out of the waveguide at all. Although, one could limit the contact area of the thermal interface material and the silicon photonic integrated circuit device, such as at a periphery thereof, this will constrain the heat flow path and result in lower cooling efficiency. Thus, cooling photonic integrated circuit devices is a significant challenge.
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
The terms “over”, “to”, “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The term “package” generally refers to a self-contained carrier of one or more dice, where the dice are attached to the package substrate, and may be encapsulated for protection, with integrated or wire-bonded interconnects between the dice and leads, pins or bumps located on the external portions of the package substrate. The package may contain a single die, or multiple dice, providing a specific function. The package is usually mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components, forming a larger circuit.
Here, the term “cored” generally refers to a substrate of an integrated circuit package built upon a board, card or wafer comprising a non-flexible stiff material. Typically, a small printed circuit board is used as a core, upon which integrated circuit device and discrete passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials.
Here, the term “coreless” generally refers to a substrate of an integrated circuit package having no core. The lack of a core allows for higher-density package architectures, as the through-vias have relatively large dimensions and pitch compared to high-density interconnects.
Here, the term “land side”, if used herein, generally refers to the side of the substrate of the integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term “die side”, which is the side of the substrate of the integrated circuit package to which the die or dice are attached.
Here, the term “dielectric” generally refers to any number of non-electrically conductive materials that make up the structure of a package substrate. For purposes of this disclosure, dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dice mounted on the substrate.
Here, the term “metallization” generally refers to metal layers formed over and through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of a package substrate may be confined to a single layer or in multiple layers separated by layers of dielectric.
Here, the term “bond pad” generally refers to metallization structures that terminate integrated traces and vias in integrated circuit packages and dies. The term “solder pad” may be occasionally substituted for “bond pad” and carries the same meaning.
Here, the term “solder bump” generally refers to a solder layer formed on a bond pad.
The solder layer typically has a round shape, hence the term “solder bump”.
Here, the term “substrate” generally refers to a planar platform comprising dielectric and metallization structures. The substrate mechanically supports and electrically couples one or more IC dies on a single platform, with encapsulation of the one or more IC dies by a moldable dielectric material. The substrate generally comprises solder bumps as bonding interconnects on both sides. One side of the substrate, generally referred to as the “die side”, comprises solder bumps for chip or die bonding. The opposite side of the substrate, generally referred to as the “land side”, comprises solder bumps for bonding the package to a printed circuit board.
Here, the term “assembly” generally refers to a grouping of parts into a single functional unit. The parts may be separate and are mechanically assembled into a functional unit, where the parts may be removable. In another instance, the parts may be permanently bonded together. In some instances, the parts are integrated together.
Throughout the specification, and in the claims, the term “connected” means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
The term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, magnetic or fluidic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
The vertical orientation is in the z-direction and it is understood that recitations of “top”, “bottom”, “above” and “below” refer to relative positions in the z-dimension with the usual meaning. However, it is understood that embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
Views labeled “cross-sectional”, “profile” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.
Embodiments of the present description relate to the removal of heat from a silicon photonic integrated circuit device, wherein the removal of heat is facilitated with an optically compatible thermal interface structure thereon. The thermal interface structures may comprise stack-up designs, including an optical isolation structure and a thermal interface material, which reduces light coupling effects, while effectively conducting heat from the silicon photonic integrated circuit device to a heat dissipation device, thereby allowing effective management of the temperature thereof.
As further shown in
In one embodiment of the present description, at least one of the integrated circuit devices 200, 210, 220, and 230 may be electrically attached to the package substrate 110 in a configuration generally known as a flip-chip or controlled collapse chip connection (“C4”) configuration. In another embodiment of the present description (not shown), the silicon photonic integrated circuit devices 200 may be electrically attached to the package substrate 110 in an “open cavity” configuration, wherein the silicon photonic integrated circuit devices 200 are at least partially embedded in the package substrate 110 that allows for direct attachment of the silicon photonic integrated circuit devices 200 to electronic integrated chips 210 (a controller for the silicon photonic integrated circuit devices 200) for better power efficiency and allows for less obstructed access to the silicon photonic integrated circuit device for the attachment of the optical communication cables 150.
The package substrate 110 may comprise a plurality of dielectric material layers (not shown), which may include build-up films and/or solder resist layers, and may be composed of an appropriate dielectric material, including, but not limited to, bismaleimide triazine resin, fire retardant grade 4 material, polyimide material, silica filled epoxy material, glass reinforced epoxy material, low temperature co-fired ceramic materials, and the like, as well as low-k and ultra low-k dielectrics (dielectric constants less than about 3.6), including, but not limited to, carbon doped dielectrics, fluorine doped dielectrics, porous dielectrics, organic polymeric dielectrics, fluoropolymers, and the like.
The package substrate 110 may further include conductive routes or “metallization” (not shown) extending through the package substrate 110 for the interconnection of the integrated circuit devices 200, 210, 220, and 230 and/or for the interconnection of the package substrate 110 to an external board (not shown). These conductive routes (not shown) may be a combination of conductive traces (not shown) formed between the dielectric material layers (not shown) and conductive vias (not shown) extending through the dielectric material layers (not shown). The structure and fabrication of conductive traces and conductive vias are well known in the art and are not shown or described for purposes of clarity and conciseness. The conductive traces and the conductive vias may be made of any appropriate electrically conductive material, including, but not limited to, metals, such as copper, silver, nickel, gold, and aluminum, alloys thereof, and the like. As will be understood to those skilled in the art, the package substrate 110 may be a cored substrate or a coreless substrate.
As shown in
The heat dissipation device 300 may comprise any appropriate thermally conductive structure, including but not limited to an integrated heat spreader, a heat sink, a heat pipe, a thermoelectric cooler, a cold plate, and the like, and may be made of any appropriate thermally conductive material, including, but not limited to, metals, such as copper, silver, nickel, gold, and aluminum, alloys thereof, and the like. In one embodiment of the present description, the heat dissipation device 300 may include a cut-out window or notch therein to allow for a less obstructed access to the silicon photonic integrated circuit device for the attachment of the optical communication cables 150.
As shown in
In one embodiment of the present description, the light insulating die attach film 410 may have a thickness T2 of between about 5 and 20 microns, but not limited thereto. The rule of thumb is that the minimum thickness T2 needs to be at least two times larger than the mode field diameter of communication structures on the first surface 202 in order to effectively insulate light. As will be understood to those skilled in the art, the maximum thickness T2 of the light insulation die attach film 410 will depend on desired parameter goals. For example, as the thermal conductivity of die attach films are typically relatively low (e.g., between about 0.2 and 0.4 watts per meter*Kelvin), a thinner film closer to 5 microns may result in a lower thermal resistance and may be preferred in most cases for more efficient heat removal. However, in order to accommodate larger packages and potential warpage, a thicker film of closer to 20 microns may be chosen to accommodate such warpage.
The silicon heat spreader 420 may contact the light insulating die attach film 410 to adhere it to the silicon photonic integrated circuit device 200 for improved heat removal. As the light insulating die attach film 410 optically isolates the first surface 202 of the silicon photonic integrated circuit device 200, the silicon heat spreader 420 will not cause light absorption, scattering, and/or coupling. Furthermore, the silicon heat spreader 420 will have substantially the same coefficient of thermal expansion as the silicon photonic integrated circuit device 200 to minimize thermally induced mechanical stresses that could damage components of the silicon photonic integrated circuit device 200.
The thermal interface material layer 430 may be disposed between the silicon heat spreader 420 and the heat dissipation device 300 for thermal coupling therebetween. As the thermal interface material layer 430 is between the silicon heat spreader 420 and the heat dissipation device 300, and does not contact the silicon photonic integrated circuit device, the thermal interface material layer 430 may be any appropriate thermally conductive material, filled or unfilled.
As will be understood, before the assembly of the electronic assembly 100 (see
As shown in
In an embodiment of the present description, the compliant thermal interface pad 520 may be disposed between the silicon plateau 510 of the silicon photonic integrated circuit device 200 and the heat dissipation device 300. In one embodiment, the compliant thermal interface pad 520 is sufficiently conformable, resilient, and/or deformable is to reduce loading stress from the heat dissipation device 300 to the silicon photonic integrated circuit device 200, which may damage components within the silicon photonic integrated circuit device 200 or even crack the silicon photonic integrated circuit device 200 itself. Furthermore, in an embodiment of the present description, the compliant thermal interface pad 520 may be sufficiently rigid to prevent it from extending too far into the air gap 270 over the waveguide area 260. It is understood that the compliant thermal interface pad 520 may partially extend into the air gap 270, as long as there is a distance of two times the “mode field diameter (MFD)” between the first surface 202 over the waveguide area 260 and the thermal interface pad 520. In one embodiment, the compliant thermal interface pad 520 may include, but is not limited to, gap filler material (such as silicone rubber carrier material containing thermally conductive ceramic filler particles), thermally conductive elastomer, vertical carbon thermal interface material, and the like.
In an embodiment of the present description, as shown in
In one embodiment of the present description, the thermal interface tape 620 may include, but is not limited to, gap filler material (such as silicone rubber carrier material containing thermally conductive ceramic filler particles), thermally conductive elastomer, vertical carbon thermal interface material, and the like. In another embodiment of the present description, the thermal interface tape 620 can be replaced by thermal grease or a polymer thermal interface material.
As will be understood, the thermal interface structure 600 may be pre-attached to the heat dissipation device 300 for easier handling, as shown in
The communication chip enables wireless communications for the transfer of data to and from the computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
At least one of the integrated circuit components may include an integrated circuit package, which comprises a package substrate, wherein the package substrate includes a first surface; a heat dissipation structure within the package substrate; and a photonic integrated circuit device, wherein the silicon photonic integrated circuit device is attached adjacent to the first surface of the package substrate and thermally coupled to the heat dissipation structure.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in
The following examples pertain to further embodiments and specifics in the examples may be used anywhere in one or more embodiments, wherein Example 1 is an apparatus, comprising a photonic integrated circuit device, wherein the photonic integrated circuit device has a first surface; an optical isolation structure proximate the first surface of the photonic integrated circuit device; a thermal interface material on the optical isolation structure; and a heat dissipation device, wherein the heat dissipation device is thermally coupled to the thermal interface material.
In Example 2, the subject matter of Example 1 can optionally include the optical isolation structure comprising a light insulating die attach film.
In Example 3, the subject matter of Example 2 can optionally include the light insulation die attach film being selected from the group consisting of polymers, silicones, acrylates, epoxies, rubbers, fused silicas, and acrylics.
In Example 4, the subject matter of any of Examples 2 to 3 can optionally include the light insulation die attach film containing no filler material.
In Example 5, the subject matter of any of Examples 2 to 3 can optionally include the light insulation die attach film comprising silica filler particles and having a refraction index substantially matching the refraction index of the silica filler particles.
In Example 6, the subject matter of any of Examples 1 to 5 can optionally include a heat spreader between the light insulation die attach film and the thermal interface material.
In Example 7, the subject matter of Example 1 can optionally include the optical isolation structure comprising an air gap.
In Example 8, the subject matter of Example 7 can optionally include the air gap being formed in the photonic integrated circuit device.
In Example 9, the subject matter of Example 8 can optionally include the air gap being formed in a plateau formed in the photonic integrated circuit device.
In Example 10, the subject matter of any of Examples 7 to 9 can optionally include the thermal interface material comprising a compliant thermal interface pad.
In Example 11, the subject matter of Example 10 can optionally include the compliant thermal interface pad being selected from the group consisting of gap filler material, thermally conductive elastomer, and vertical carbon thermal interface material.
In Example 12, the subject matter of Example 1 can optionally include the optical isolation structure comprising a cladding material layer.
In Example 13, the subject matter of Example 12 can optionally include the cladding material layer being selected from the group consisting of polymers, silicones, acrylates, epoxies, and acrylics.
In Example 14, the subject matter of any of Examples 12 to 13 can optionally include the thermal interface material comprising a thermal interface tape.
In Example 15, the subject matter of Example 10 can optionally include the compliant thermal interface pad being selected from the group consisting of gap filler material, thermally conductive elastomer, and vertical carbon thermal interface material.
Example 16 is an apparatus, comprising a package substrate, wherein the package substrate includes a first surface; a photonic integrated circuit device electrically attached to the package substrate, wherein the photonic integrated circuit device has a first surface; an optical isolation structure proximate the first surface of the photonic integrated circuit device; a thermal interface material on the optical isolation structure; and a heat dissipation device, wherein the heat dissipation device is thermally coupled to the thermal interface material.
In Example 17, the subject matter of Example 16 can optionally include the optical isolation structure comprising a light insulating die attach film.
In Example 18, the subject matter of Example 17 can optionally include the light insulation die attach film being selected from the group consisting of polymers, silicones, acrylates, epoxies, rubbers, fused silicas, and acrylics.
In Example 19, the subject matter of any of Examples 17 to 18 can optionally include the light insulation die attach film containing no filler material.
In Example 20, the subject matter of any of Examples 17 to 18 can optionally include the light insulation die attach film comprising silica filler particles and having a refraction index substantially matching the refraction index of the silica filler particles.
In Example 21, the subject matter of any of Examples 16 to 20 can optionally include a heat spreader between the light insulation die attach film and the thermal interface material.
In Example 22, the subject matter of Example 16 can optionally include the optical isolation structure comprising an air gap.
In Example 23, the subject matter of Example 22 can optionally include the air gap being formed in the photonic integrated circuit device.
In Example 24, the subject matter of Example 23 can optionally include the air gap being formed in a plateau formed in the photonic integrated circuit device.
In Example 25, the subject matter of any of Examples 22 to 24 can optionally include the thermal interface material comprising a compliant thermal interface pad.
In Example 26, the subject matter of Example 25 can optionally include the compliant thermal interface pad being selected from the group consisting of gap filler material, thermally conductive elastomer, and vertical carbon thermal interface material.
In Example 27, the subject matter of Example 16 can optionally include the optical isolation structure comprising a cladding material layer.
In Example 28, the subject matter of Example 27 can optionally include the cladding material layer being selected from the group consisting of polymers, silicones, acrylates, epoxies, and acrylics.
In Example 29, the subject matter of any of Examples 27 to 28 can optionally include the thermal interface material comprising a thermal interface tape.
In Example 30, the subject matter of Example 29 can optionally include the compliant thermal interface tape being selected from the group consisting of gap filler material, thermally conductive elastomer, and vertical carbon thermal interface material.
In Example 31, the subject matter of Example 16 to 30 can optionally include an optical communication cable attached to the photonic integrated circuit device.
Example 32 is an electronic system, comprising an electronic board and an integrated circuit package electrically attached to the electronic board, wherein the integrated circuit package comprises a package substrate, wherein the package substrate includes a first surface; a photonic integrated circuit device electrically attached to the package substrate, wherein the photonic integrated circuit device has a first surface; an optical isolation structure proximate the first surface of the photonic integrated circuit device; a thermal interface material on the optical isolation structure; and a heat dissipation device, wherein the heat dissipation device is thermally coupled to the thermal interface material.
In Example 33, the subject matter of Example 32 can optionally include the optical isolation structure comprising a light insulating die attach film.
In Example 34, the subject matter of Example 33 can optionally include the light insulation die attach film being selected from the group consisting of polymers, silicones, acrylates, epoxies, rubbers, fused silicas, and acrylics.
In Example 35, the subject matter of any of Examples 33 to 34 can optionally include the light insulation die attach film containing no filler material.
In Example 36, the subject matter of any of Examples 33 to 34 can optionally include the light insulation die attach film comprising silica filler particles and having a refraction index substantially matching the refraction index of the silica filler particles.
In Example 37, the subject matter of any of Examples 32 to 36 can optionally include a heat spreader between the light insulation die attach film and the thermal interface material.
In Example 38, the subject matter of Example 32 can optionally include the optical isolation structure comprising an air gap.
In Example 39, the subject matter of Example 38 can optionally include the air gap being formed in the photonic integrated circuit device.
In Example 40, the subject matter of Example 39 can optionally include the air gap being formed in a plateau formed in the photonic integrated circuit device.
In Example 41, the subject matter of any of Examples 38 to 40 can optionally include the thermal interface material comprising a compliant thermal interface pad.
In Example 42, the subject matter of Example 41 can optionally include the compliant thermal interface pad being selected from the group consisting of gap filler material, thermally conductive elastomer, and vertical carbon thermal interface material.
In Example 43, the subject matter of Example 32 can optionally include the optical isolation structure comprising a cladding material layer.
In Example 44, the subject matter of Example 43 can optionally include the cladding material layer being selected from the group consisting of polymers, silicones, acrylates, epoxies, and acrylics.
In Example 45, the subject matter of any of Examples 43 to 44 can optionally include the thermal interface material comprising a thermal interface tape.
In Example 46, the subject matter of Example 45 can optionally include the compliant thermal interface tape being selected from the group consisting of gap filler material, thermally conductive elastomer, and vertical carbon thermal interface material.
In Example 47, the subject matter of Example 32 to 46 can optionally include an optical communication cable attached to the photonic integrated circuit device.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
This invention was made with government support from the United States Government under Agreement No. HR0011-19-3-0003, awarded by the Defense Advanced Research Projects Agency (DARPA). The Government has certain rights in the invention.
