Patent Application
20060090885
The field of invention relates generally to heat removal; and, more specifically, to an improved thermally conductive channel between a semiconductor chip and an external thermal interface
The power consumption of electrical circuitry has emerged as, perhaps, the single largest threat to the continued advancement of semiconductor technology and its ability to craft new markets through the shrinking of transistor device size. Simply put, the smaller a transistor can be made, the more power will be consumed per transistor (owing to the transistor's faster speed and substrate leakage) and the more transistors can be fit onto a single chip of silicon. The combination of more transistors per chip and greater power consumption per transistor has resulted in some of the more advanced semiconductor chips under development exhibiting excessive heat dissipation.
Therefore, semiconductor chip developers are devoting significant resources to the study and development of higher performance yet cost effective chip cooling technologies. Traditionally, cost effective chip cooling has meant “air-cooled” heat sinks.
As a general perspective, chip cooling technologies are actually more accurately viewed as a heat removal systems. Here, heat generated by a semiconductor chip is transferred to an “external thermal interface”; and, then, the external thermal interface “externally” convects, conducts or radiates the heat to some medium (typically air) that is not deemed part of the semiconductor chip and its associated packaging. Here, the ability to transfer heat “externally” from the semiconductor chip and its packaging corresponds, in turn, to its cooling.
According to air-cooled heat sink approaches, the external thermal interface is a heat sink made of thermally conductive fins that rise above the surface of the semiconductor chip's package. The heat dissipated by a semiconductor chip is channeled to the heat sink's fins. As a general rule, cooling efficiency improves as the surface area of a heat transferring material increases. With respect to heat sinks, the fins of the heat sink effectively create an expanded external thermal interface surface area over which the semiconductor chip's heat is externally convected and/or radiated.
When air is blown through the heat sink's fins, heat is transferred from the fins to the air so as to effectively remove heat from the semiconductor chip and its associated packaging. Unfortunately, the traditional air-cooled mechanism described above—although cost effective—may not exhibit sufficient performance for future high performance and/or high density semiconductor chips.
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
a and 1b show semiconductor chips and their respective hot spots;
a and 1b attempt to graphically depict a particular challenge that, if overcome, could possibly lead to higher performance yet reasonably affordably chip cooling technologies. The particular challenge is uniformly spreading out heat generated from specific regions of the chip that generate excessive heat (commonly referred to as “hot spots”) as the heat is carried to the external thermal interface.
a shows a temperature profile of a first semiconductor chip and
Hot spots are generally created by regions of circuitry operating at high speed. Typically, a digital circuit region will tend to generate more heat as its constituent transistors: 1) are packed more densely; 2) operate faster, and, 3) push/pull more current. The smallest rings observed in
Owing to inefficiencies in the thermal channel that exists between a semiconductor chip and its heat sink, present day generically designed heat sink approaches do not respond well to semiconductor chip “hot spots”. More precisely stated, the thermal conductive channel that exists between the external thermal interface (i.e., the heat sink) and the semiconductor chip conducts heat from different regions of the chip differently. As such, certain regions of the semiconductor chip will enjoy lower thermal resistance between themselves and the external thermal interface than other less fortunate regions.
If a “hot spot” happens to reside in a region that does not enjoy lower thermal resistance between itself and the external thermal interface, the effected heat transfer from the hot spot may be insufficient to keep the semiconductor chip within acceptable thermal operating limits. The problem can be lessened at least somewhat by custom designing the thermal conductive channel between the semiconductor chip and the external thermal interface on a chip-design by chip-design basis.
Thus, for example, a first conductive channel could be designed for the semiconductor chip of
Importantly, the vapor molecules scatter randomly within the chamber 207. As such, the location where a vapor molecule condenses on the lid underside 211 should be effectively random relative to the semiconductor chip region whose heat nucleated the vapor molecule.
Thus, through this process, heat generated from a particular semiconductor chip region should be uniformly distributed across the lid underside 211. All regions of the semiconductor chip should therefore enjoy approximately the same thermal resistance between themselves and the external thermal interface; and, as a result, custom thermal packaging solutions can be avoided. Immediately following is a more thorough discussion of the principles of operation of the technique depicted in
According to the depiction of
Any thermally conductive stud will radiate heat generated by the semiconductor chip in a region of the semiconductor chip 201 that is, approximately, directly beneath the stud. The thermal transfer properties of the thermally conductive studs are similar to those described in the background with respect to heat sink implementations. That is, the efficiency of heat transfer from the semiconductor chip 201 into the liquid 208 is improved because the thermally conductive studs effectively correspond to a greater surface area of the chamber's floor layer 203.
For simplicity, these regions 2101, 2102 have been drawn to include nucleated “bubbles” that result from heat being transferred from the studs within regions 2101, 2102 residing above hot spots 2091, 2092 into liquid 208. That is, the liquid inside regions 2101, 2102 have been depicted as boiling above hot spots 2091, 2092. It should be understood that in many practical implementations the design point of operation within the chamber is expected to be simply that the liquid above a hot spot will nucleate bubbles 208 more rapidly than other “non hot spot” regions.
As discussed above in some detail, the vaporization of the liquid 208 above the hot spot regions 2091, 2092 will result in the generation of vapor molecules above the liquid 208 within region 207 of the chamber. Owing to their high kinetic energy, the vapor molecules will effectively travel randomly within chamber region 207, resulting in the condensation of at least some vapor molecules on the “ceiling” of the chamber 211 (note “drops” of liquid such as drops 212). The spread or distribution on the ceiling 211 of condensing vapor molecules that were generated from a particular region of the liquid (e.g., those from region 2101) is expected to be largely random. Hence, heat generated from a particular hot spot (e.g., hot spot 2091) is expected to be randomly distributed across the ceiling 211 of the chamber.
Because the heat from a particular hot spot is uniformly distributed across the ceiling 211 of the chamber, the heat transfer from the particular hot spot is effectively distributed more uniformly to the external thermal interface. Importantly, this principle should apply to any hot spot irregardless of its location. As such, the approach of
In one embodiment, the chamber is first formed prior to its attachment to the semiconductor die 201. For example, walls 204, 205 are affixed to a first layer of material used for floor layer 203. Then, liquid is added to the chamber and lid 206 is applied over walls 204, 205 to seal the chamber. In an embodiment, the floor layer 203, walls 204, 205 and lid 206 are each comprised of Silicon (Si). In a further embodiment, a Si lid 206 is directly bonded to the Si chamber walls. The liquid may be comprised of various solutions such as water, alcohols, refrigerants or flourinerts such as FC-77.
In further or related embodiments the lid 206 has its exterior surface “processed” for efficient thermal coupling to an external thermal interface such as a heat sink. For example, the top surface of the lid 206 may be micro-machined or etched to effectively increase its surface area. Moreover or in the alternative, a layer 214 of thermally conductive material (e.g., metal) may be coated on the top surface of the lid 206. The coating 214 may be a multi-layer structure such as a first layer of metal beneath a second Indium alloy layer.
The studs 213 of floor layer 203 are comprised, in at least one embodiment, of carbon nanotubes. Here, it is generally understood in the art that carbon nanotubes may have different electrical properties. Examples include “conducting” and “semiconducting” carbon nanotubes. Generally, similar to other conducting materials, conducting carbon tubes have high thermal conductivities. Thus, in a further embodiment, the studs 213 of floor layer 203 include conducting carbon nanotubes. The use of conducting carbon nanotubes (as opposed to, for example, insulating carbon nanotubes) should enhance the transfer of heat from chamber floor layer 203 to liquid 208.
According to at least one approach, a chamber floor layer 203 with conducting carbon nanotubes 213 is formed by growing vertically oriented carbon nanotubes upon a substrate (such as a substrate comprised of Si). The substrate is used to implement chamber floor layer 203 and the vertically grown conducting carbon nanotubes correspond to studs 213.
Processes for vertically growing carbon nanotubes on a substrate (such as a substrate comprised of Si) have already been published in the art, see Z. Y. Juang, et al., 2004, “The effects of ammonia on the growth of large-scale patterned aligned carbon nanotubes using thermal chemical vapor deposition method”, Diamond and Related Materials, Vol, 13, no. 4-8 pp. 1203-1209; H. Konishi, et al., 2004, “Growth control of carbon nanotubes on silicon carbide surfaces using the laser irradiation effect”, Thin Solid Films, Vol. 464-465, pp. 295-298, and Ki-Hong Lee, et al., 2004, “Silicon enhanced carbon nanotube growth on nickel films by chemical vapor deposition” Solid State Communications, Vol. 129, No. 9, pp. 583-587, each of which presents different methods for the growth of carbon nanotubes on various types of surfaces.
According to one carbon nanotube growth technique, carbon nanotubes are spontaneously grown by placing a substrate coated with Nickel (Ni) into a plasma furnace containing ammonia gas and acetylene. A controlled electrical arc is passed through the sample, spontaneously causing growth of aligned nanotubes, see Z. F. Ren et al., 1998, “Synthesis of Large Arrays of Well-Aligned Carbon Nanotubes on Glass”, Science, Vol. 282, pp. 1105-1107.
Another interesting feature of using vertically oriented carbon nanotubes for studs 213 is the granularity at which the carbon nanotubes might be displaced on the surface of the chamber floor. To the extent that the heights reached by the vertically oriented carbon tubes are “short” and, as a consequence, their role of effectively increasing the surface area of the chamber floor layer 203 is less than impressive, note that that their lack of height is at least partially compensated for by the density at which they can be packed together. That is, given that carbon nanotubes are extremely small particles, they add to the effective surface area of the chamber floor layer 203 more by the number of surface perturbations that they effect rather than by the height of these perturbations.
Note that each of items 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, and 314 can behave similar to their respective counterparts 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, and 214 discussed with respect to
The die may be any type of die product such as a processor (e.g., general purpose processor, digital signal processor), memory device (e.g., Static Random Access Memory (SRAM) chip; Dynamic Random Access Memory (DRAM) chip) or non standard product offering Application Specific Integrated Circuit (ASIC) (i.e., a semiconductor chip not sold on the open market with its own part number or other identifier that identifies the chip alone) such as those commonly used to implement the switching and/or routing function within networking hardware equipment (e.g., switches, routers).
Atop the die 401, the complete chamber 400 containing liquid is shown. A cross section of the die 401 and chamber 400 may be as depicted in
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
