"A Novel Planar Multilevel Interconnection Technology Utilizing Polyimide", K. Sato et al., IEEE Trans. Part Hybrid Package. PHP-9, 176, Sep. 1973. |
"A Planarization Process for Double Metal CMOS Using Spin-on Glass as a Sacrificial Layer", P. Elikins et al., proceeding of 3rd International IEEE VMIC Conf., 100, Jun. 9-10, 1986. |
"Planar Interconnection Technology for LSI Fabrication Utilizing Lift-Off Process", K. Ehara et al., J. Electrochem. Soc., vol. 131. No. 2, 419, Feb. 1984. |
"Study of Planarized Sputter-Deposited Si0.sub.2 " C.Y. Ting et al., J. Vac. Sci. Technol. 15, 1105, Feb. 16, 1978. |
"Si0.sub.2 Planarization Technology with Biasing and Electron Cyclotron Resonance Plasma Deposition for Submicron Interconnections", K. Machida et al., J. Vac. Sci Technol B4, 818, Jul./Aug. 1986. |
"Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections", W.J. Patrick et al., J. Electrochem. Soc., vol. 138, No. 6, Jun. 1991. |