1. Field of the Invention
The present invention relates to a thin film resistor structure, and more particularly, to a thin film resistor structure integrated with a metal gate structure.
2. Description of the Prior Art
In the field of semiconductor fabrication, polysilicon material has been conventionally used to form the gates of metal-Oxide-Semiconductor Field-Effect (MOSFET) transistors. However, polysilicon materials have some drawbacks: the resistance of a polysilicon gate is higher than most of any metal materials, and the conductivity rate of the polysilicon gate is therefore lower than metal wires. In order to compensate for this disadvantage, the polysilicon gate usually undergoes a silicide process to simultaneously reduce the contact resistance and the parasitic resistance (Rp), so that the conductivity rate of the polysilicon gate is improved to an acceptable range.
It is worth noting that the polysilicon is used not only to form the gates, but also to form passive devices for mixed-mode integrated circuit devices, such as capacitors, or thin film resistors, etc. It is also well-known that the resistance of a thin film resistor made of polysilicon can be adjusted by modifying factors such as temperature or pressure during the polysilicon deposition process, or by adjusting the area, the thickness, or the concentration of implanted dopants in the polysilicon layer.
Nevertheless, in the trend to replace the polysilicon gates with metal gates, those integrated passive devices that used to be made of polysilicon are also replaced with metal materials ones. Similarly to the formation process of the active devices, passive devices such as thin film resistor are fabricated by integrating the formation of the metal layer and the dielectric layer, the photolithography process, and the etching process. It is conceivable that the integration of the metal thin film resistor process and the metal gate process, particularly a gate-first process, is more complicated, and the control of the thickness and composition of the materials in use is more difficult.
Therefore looking for a way to integrate the metal gate and the thin film resistor without increasing the process complexity and costs for such strict requirements has become an important study in this field.
A thin film resistor integrated with a metal gate structure is provided for the present invention.
According to one preferred embodiment of the present invention, a thin film resistor structure is provided, comprising a substrate, a flat bottom ILD (inter layer dielectric) disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, wherein each top surface of the first contacts is on the same level as a top surface of the bottom ILD, a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, wherein each top surface of the second contacts is on the same level as a top surface of the top ILD, and a thin film resistor disposed between the bottom ILD and the top ILD.
The present invention further provides a thin film resistor structure comprising a substrate, a flat bottom ILD disposed on the substrate, a plurality of first contacts disposed in the bottom ILD, wherein each top surface of the first contacts is on the same level as a top surface of the bottom ILD, a flat top ILD disposed on the bottom ILD, a plurality of second contacts disposed in the top ILD, wherein each top surface of the second contacts is on the same level as a top surface of the top ILD, a thin film resistor disposed between the bottom ILD and the top ILD; and at least a supporting material disposed under the thin film resistor within the bottom ILD.
To summarize the above descriptions, the present invention provides a thin film resistor structure with a simplified manufacturing process compared to the conventional polysilicon resistor. Besides, the thin film resistor is disposed between two ILD (inter layer dielectric). The structure can be integrated with a high-k metal gate process, and doesn't need complicated additional processes.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
To provide a better understanding of the present invention to users skilled in the technology of the present invention, preferred embodiments are detailed as follows. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements to clarify the contents and effects to be achieved.
Please refer to
A polysilicon gate (not shown) is formed within the semiconductor region 102 as a dummy gate, and after a light doped drain (LDD), a spacer, a source/drain and a dielectric layer are formed, the polysilicon gate is replaced with a metal gate by a gate replacement process and a contact plug process. A bottom ILD (inter layer dielectric) 110 is entirely formed on the substrate 100 by a planarization process such as CMP (chemical mechanical polishing). After that, a plurality of first contacts 130 is formed in the bottom ILD 110 within the semiconductor region 102. Up to present step, as shown in
The metal gate 112 includes a high-k layer 116 and at least a metal layer 118, wherein the high-k layer 116 is disposed between the substrate 100 and the metal layer 118, it may selected from a group comprising hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1—XTiO3, BST). The metal layer 118 may be adjusted according to the metal gate 112 for PMOS or NMOS use, each of them having specific bottom barriers, work function layer, top barriers and main conductive layer. Moreover, the first contact 130 may be formed during the gate replacement process simultaneously, so that the first contact 130 and the metal gate 112 have the same materials in the work function layer and the main conductive layer, such as aluminum (Al), tungsten (W), copper (Cu), titanium aluminide (TiAl), titanium (Ti), titanium nitride (TiN), tantalum (Ta), Tantalum nitride (TaN) and titanium aluminum oxide (TiAlO). Besides, the spacer 120 may be a single layer structure or a multilayer structure formed by materials such as silicon nitride or silicon oxide, and at least a first doping region 114 formed in the substrate 100 at least one side of the metal gate 112, the doping region 114 may includes an epitaxial layer such as a silicon germanium epitaxial layer or a silicon carbide epitaxial layer, and a metal silicide (not shown) may be further formed on the doping region 114 to improve the contact performances. In addition, a CESL (contact etch stop layer, CESL) 122 may be formed between the substrate 100 and the bottom ILD 110.
It is worth noting that the embodiment is described with a high-k gate last process, but not limited thereto, the present invention may also use a high-k first gate last process, a high-k gate first process or a polysilicon gate process, and the related technologies are well known by users skilled in the technology, not redundantly described here.
Afterwards, as shown in
As shown in
As shown in
The following description will describe the different embodiments of the thin film transistor device and the manufacturing method of the present invention. To simplify the description, the following description will focus on the dissimilarities among the different embodiments and the identical features will not be redundantly described. For making it easier to compare the differences between the embodiments, the identical components in each of the following embodiments are marked with identical symbols.
Please refer to
As shown in
It is worth noting that the difference between the second preferred embodiment and the first preferred embodiment is that in the latter one, each metal gate and the first contacts are not only within the semiconductor region 102, but also within the resistor region 104. The metal gate structure 113 or the first contacts 131 within the resistor region 104 are used as a supporting material 160. In other words, the supporting material 160 comprises the supporting metal gate 113 or the first contact 131 located in the resistor region 104. And the metal gate structure 113 or the first contact 131 may be a floating structure electrically isolated from other elements. The supporting material 160 is right under the thin film resistor 134 and serves as a support pillar that avoids dishing effects caused during the performing of the CMP on a large area of the bottom ILD 110 in the gate replacement process and the contact plug process. The second stop layer 132 and the thin film resistor layer 134 may be influenced by the dishing too. Since the supporting material 160 and the metal gate structure 112 or the first contacts 130 are formed simultaneously, there is no additional cost in this embodiment.
It is worth noting that the supporting material 160 comprises all the elements disposed under the thin film resistor 160 and in the bottom ILD 110. The supporting material 160 includes the metal gate structure 113, the first contact 131 and even the dummy gate formed before the metal gate structure 113. All of these may be the supporting material 160. Besides, a surface of the supporting material substantially contacts the second stop layer 132 or the second contact 150, and a bottom surface of the supporting material substantially contacts the substrate 100, the STI 106 or the doping region 114 according to the situation. As shown in
Besides,
To summarize the above descriptions, the invention provides a thin film resistor structure having a thin film resistor disposed between two flat ILD (inter layer dielectric). The structure can be integrated with a high-k metal gate process, and doesn't need complicated additional processes. Besides, another embodiment of the present invention provides a plurality of supporting materials disposed under the thin film resistor within the bottom ILD to avoid dishing.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
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