Patent Application
20230352581
The disclosure relates to microelectronic devices including semiconductor devices, transistors, and integrated circuits, including methods of microfabrication.
In the manufacture of a semiconductor device (especially on the microscopic scale), various fabrication processes are executed such as film-forming depositions, etch mask creation, patterning, material etching and removal, and doping treatments. These processes are performed repeatedly to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors have been created in one plane, with wiring/metallization formed above the active device plane, and have thus been characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, yet scaling efforts are running into greater challenges as scaling enters single digit nanometer semiconductor device fabrication nodes. Semiconductor device fabricators have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.
3D integration, i.e., the vertical stacking of multiple devices, aims to overcome scaling limitations experienced in planar devices by increasing transistor density in volume rather than area. Although device stacking has been successfully demonstrated and implemented by the flash memory industry with the adoption of 3D NAND, application to random logic designs is substantially more difficult. 3D integration for logic chips (CPU (central processing unit), GPU (graphics processing unit), FPGA (field programmable gate array, SoC (System on a chip)) is being pursued.
Techniques herein include methods and devices for 3D fabrication of semiconductor devices. Specifically, logic circuits and memory circuits can be built based on vertical field effect transistor (VFET) structures with self-aliened processing. In the disclosure, low Dt process can be integrated as standalone devices or 3D sequential circuit builds. A deposited channel region (e.g., conductive oxides) can be utilized as 3D building block stacks for N devices tall. The deposited channel region may have metal layers beneath the device to enable source and drain connections. Channel geometries made of conductive oxides can be deposited and etched to form a 3D network of vertical nano sheets. Thus, no epitaxial silicon is required during the process. In the disclosure, complemental field effect transistor (CFET) and side by side CMOS devices can be implemented based on the disclosed VFET structures. Polarity of the VFET stacks can be varied as p-type or n-type. In addition, gate all around (GAA), different High-k, gate metal as well as source/drain metal can be used as options. Further, buried power rail and meal routing between VFET stacks can be applied. In the disclosure, two different flows can be implemented to create VFET stacks. Very low off state leakage and robust transistor properties can be obtained with this conductive oxide stack design.
In a first manufacturing flow of the disclosure, a metal first layer design for fabricating transistors with conductive oxide layers is provided. Pre-aligned mask can be applied for easy etching trench to fabricate device. Accordingly, alignment offset of 3 different masks has no effect or impact on device performance.
In a second manufacturing flow, a number of stacks of conductive oxide nanosheet can be provided. Polarity of the stack can be varied as p-type or n-type. Different High-k, gate metal as well as source/drain metal can be used as options.
Of course, an order of the manufacturing steps disclosed herein is presented for clarity sake. In general, these manufacturing steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. herein may be discussed in different places of the present disclosure, it should be noted that each of the concepts can be executed independently from each other or in combination with each other. Accordingly, the present disclosure can be embodied and viewed in many different ways.
It should be noted that this summary section does not specify every embodiment and/or incrementally novel aspect of the present disclosure or claimed invention. Instead, this summary only provides a preliminary discussion of different embodiments and corresponding points of novelty over conventional techniques. For additional details and/or possible perspectives of the invention and embodiments, the reader is directed to the Detailed Description section and corresponding figures of the present disclosure as further discussed below.
According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device can include a first bottom contact positioned in a dielectric layer over a substrate, and a first channel structure extending from and in contact with the first bottom contact in a vertical direction perpendicular to the substrate. The first channel structure can include a bottom portion over the first bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor device can include a first gate structure positioned around the middle portion of the first channel structure, and a first top contact positioned over and in contact with the top portion of the first channel structure.
In some embodiments, the first channel structure can have one of a circular pillar-shape, a square pillar-shape, an oval pillar-shape, and a rectangular pillar-shape.
In some embodiments, the bottom portion of the first channel structure can have a height in a range from 5 nm to 30 nm. The top portion of the first channel structure can have a height in a range from 5 nm to 30 nm, and the first channel structure can have a height in a range from 15 nm to 90 nm.
The first gate structure can further include a first gate dielectric layer around the middle portion of the first channel structure, and a first gate electrode around the first gate dielectric layer.
The semiconductor device can include an interconnect structure positioned over the first top contact, a second bottom contact positioned over the interconnect structure, and a second channel structure extending from and in contact with the second bottom contact in the vertical direction. The second channel structure can include a bottom portion over the second bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor can also include a second gate structure positioned around the middle portion of the second channel structure, and a second top contact positioned over and in contact with the top portion of the second channel structure.
In some embodiments, the second gate structure can further include a second gate dielectric layer around the middle portion of the second channel structure, and a second gate electrode around the second gate dielectric layer.
In some embodiments, the first channel structure and the second channel structure can be made of a conductive oxide. The conductive oxide can include one of In2O3, SnO2, InGaZnO, ZnO, and SnO.
In an embodiment, the first channel structure can be made of a n-type conductive oxide and the second channel structure can be made of a p-type conductive oxide.
In another embodiment, the first channel structure can be made of a p-type conductive oxide and the second channel structure can be made of a n-type conductive oxide.
The semiconductor device can further include a third bottom contact positioned in the dielectric layer over the substrate, and a third channel structure extending from and in contact with the third bottom contact. The third channel structure can include a bottom portion over the third bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor device can include a third gate structure positioned around the middle portion of the third channel structure, and a third top contact positioned over and in contact with the top portion of the third channel structure. The third channel structure and the first channel structure can be arranged side by side over the substrate in a horizontal direction parallel to the substrate. The first top contact and the third top contact can be coupled to each other through a metal layer that is parallel to a main surface of the substrate.
According to another aspect of the disclosure, a method of forming a semiconductor device is provided. In the method, a first bottom contact can be formed in a dielectric layer over a substrate, and a first channel structure can be formed to extend from and in contact with the first bottom contact in a vertical direction perpendicular to the substrate. The first channel structure can include a bottom portion over the first bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. Further, a first gate structure can be formed around the middle portion of the first channel structure, and a first top contact can be formed over and in contact with the top portion of the first channel structure.
To form the first channel structure, an insulating layer can be formed over the dielectric layer. An opening can be formed in the insulating layer to uncover the first bottom contact. A conduct oxide can be formed in the opening to form the first channel structure.
To form the first gate structure, the insulating layer can be recessed such that the middle portion and the top portion of the first channel structure can be uncovered. A first gate dielectric layer can be formed around the middle portion and the top portion of the first channel structure. A first gate electrode can be formed around the first gate dielectric layer. The first gate dielectric layer and the first gate electrode can further be recessed such that the top portion of the first channel structure is uncovered.
To form the first top contact, an isolation layer can be formed over the insulating layer such that a top surface of the isolation layer is above a top surface of the first channel structure. An opening can be formed in the isolation layer to uncover the top surface of the first channel structure, and a conductive material can subsequently be deposited in the opening to form the first top contact.
In the method, an interconnect structure can be formed over the first top contact. A second bottom contact can be formed over the interconnect structure. A second channel structure can be formed to extend from and in contact with the second bottom contact. The second channel structure can include a bottom portion over the second bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. A second gate structure can be formed around the middle portion of the second channel structure. A second top contact can be formed over and in contact with the top portion of the second channel structure.
To form the second gate structure, a second gate dielectric layer can be formed around the middle portion of the second channel structure, and a second gate electrode can be formed around the second gate dielectric layer.
In the method, a third bottom contact can be formed in the dielectric layer. A third channel structure can be formed to extend from and in contact with the third bottom contact in the vertical direction. The third channel structure can include a bottom portion over the third bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. A third gate structure can be formed around the middle portion of the third channel structure. A third top contact can be formed over and in contact with the top portion of the third channel structure. The third channel structure and the first channel structure can be arranged side by side over the substrate in a horizontal direction parallel to the substrate. The first top contact and the third top contact can be coupled to each other through a metal layer that is parallel to a main surface of the substrate.
In some embodiments, the first channel structure and the second channel structure can be made of a conductive oxide. The conductive oxide can includes one of In2O3, SnO2, InGaZnO, ZnO, and SnO.
In some embodiments, the first channel structure can be made of one of a n-type conductive oxide and a p-type conductive oxide, and the second channel structure can be made of one of a n-type conductive oxide and a p-type conductive oxide.
In some embodiments, the bottom portion of the first channel structure can have a height in a range from 5 nm to 30 nm, the top portion of the first channel structure can have a height in a range from 5 nm to 30 nm, and the first channel structure can have a height in a range from 15 nm to 90 nm.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the apparatus in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” in various places through the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
The device 100 can include a plurality of gate structures 131 positioned around the middle portions 112B of the channel structure 112a-112d, and a plurality of top contacts 134a-134d positioned over and in contact with the top portions 112C of the channel structures 112a-112d. For example, the top contact 134a is positioned over the top portion of the channel structure 112a. Each of the gate structures 131 can further include a gate dielectric layer 132 around a respective middle portion of a channel structure, and a gate electrode 130 around the gate dielectric layer 132.
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In some embodiments, the channel structures 112a-112d can have one of a circular pillar-shape, a square pillar-shape, an oval pillar-shape, and a rectangular pillar-shape.
In some embodiments, the bottom portions 112A of the channel structures 112a-112d can have a height in a range from 5 nm to 30 nm. The top portions 112C of the channel structure 112a-112d can have a height in a range from 5 nm to 30 nm, and the channel structures 112a-112d can have a height in a range from 15 nm to 90 nm.
In the device 100, the bottom portions 112A of the channel structures 112a-112d can function as first source/drain (S/D) structures, the middle portions 112B of the channel structures 112a-112d can function as channel layers, and the top portions 112C of the channel structures 112a-112d can function as second S/D structures. Accordingly, the channel structures 112a-112d and the gate structures 131 can form a plurality of vertical field effect transistors (VFETs). The bottom contacts 110a-110d can accordingly function as interconnects to the first S/D structures of the VFETs, and the top contacts 134a can function as interconnects to the second S/D structures of the VFETs.
In some embodiments, the gate dielectric layers 132 can include SiO2, HfO2, ZrO2, HfSiNO2, ZrSiNO2, Y3O4, Si3N4, Al2O3, the like, or a combination thereof. In some embodiments, the channel structures 112a-112d can be made of a n-type conductive oxide, such as In2O3, SnO2, InGaZnO, or ZnO. The gate electrodes 130 can include a work function layer (e.g., TiC, AlTiC, AlTiO), a liner (e.g., TiN), and a filler (e.g., W or Ru). Accordingly, the VFETs can be n-type transistors. In some embodiments, the channel structures 112a-112d can be made of a p-type conductive oxide, such as SnO. The gate electrodes 130 can include a work function layer (e.g., TiON, TiC, AlTiN, AlTiC, AlTiO), a liner (e.g., TiN and/or TaN), and a filler (e.g., W or Ru). Accordingly, the VFETs can be p-type transistors.
The bottom contacts 110a-110d can include conductive material, such as Co, Ru, W, Al, and Cu. The dielectric layer 104, the insulating layer 106, and the isolation layer 108 can be made of a dielectric material, such as SiO, SiN, SiON, SiC, SiOC, SiCN, SiOCN, the like, or a combination thereof.
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The second VFET layer 200B can also include a plurality of VFETs that are stacked over the VFETs formed in the first VFET layer 200A. As shown in
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The second VFET layer 200B can include a plurality of metal lines that can connect the bottom contacts or the top contacts in the second VFET layer 200B. For example, a metal line 158 can be provided to connect the bottom contacts 146a and 146c, and a metal line 156 can be provided to connect the top contacts 154f and 154b. Thus, based on the connection between the bottom contacts and the connections between top contacts, the VFETs in the second VFET layer 200B can be connected to each other so as to form a functional circuit.
In some embodiments, the channel structures 112a-112h in the first VFET layer 200A can be made of a n-type conductive oxide, such as In2O3, SnO2, InGaZnO, and ZnO. The channel structures 148a-148h in the second VFET layer 200B can be made of a p-type conductive oxide, such as SnO. In some embodiments, the channel structures 112a-112h in the first VFET layer 200A can be made of a p-type conductive oxide, and the channel structures 148a-148h in the second VFET layer 200B can be made of a n-type conductive oxide.
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In the preceding description, specific details have been set forth, such as a particular geometry of a processing system and descriptions of various components and processes used therein. It should be understood, however, that techniques herein may be practiced in other embodiments that depart from these specific details, and that such details are for purposes of explanation and not limitation. Embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. Nevertheless, embodiments may be practiced without such specific details. Components having substantially the same functional constructions are denoted by like reference characters, and thus any redundant descriptions may be omitted.
Various techniques have been described as multiple discrete operations to assist in understanding the various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. Operations described may be performed in a different order than the described embodiment. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.
“Substrate” or “target substrate” as used herein generically refers to an object being processed in accordance with the invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronics device, and may, for example, be a base substrate structure, such as a semiconductor wafer, reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or un-patterned, but rather, is contemplated to include any such layer or base structure, and any combination of layers and/or base structures. The description may reference particular types of substrates, but this is for illustrative purposes only.
Those skilled in the art will also understand that there can be many variations made to the operations of the techniques explained above while still achieving the same objectives of the invention. Such variations are intended to be covered by the scope of this disclosure. As such, the foregoing descriptions of embodiments of the invention are not intended to be limiting. Rather, any limitations to embodiments of the invention are presented in the following claims.
