Patent Application
20230328984
The present disclosure relates generally to the field of semiconductor devices, and particularly to a three-dimensional memory device including a dummy word line with tapered corner and methods of manufacturing the same.
A three-dimensional memory device including three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
According to an aspect of the present disclosure, a memory device includes at least one alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the at least one alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. The memory opening fill structure includes a lateral protrusion having a tapered sidewall surface; and one of the electrically conductive layers is a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure.
According to another aspect of the present disclosure, a method of forming a memory device is provided, which comprises: forming at least one alternating stack over a substrate, wherein each of the at least one alternating stack comprises respective insulating layers and respective sacrificial material layers that are interlaced along a vertical direction, and wherein one of the sacrificial material layers of the at least one alternating stack comprises a composite sacrificial material layer including a primary sacrificial material sublayer including a first sacrificial material and a secondary sacrificial material sublayer including a second sacrificial material that is different from the first sacrificial material; forming a memory opening through the at least one alternating stack such that the composite sacrificial material layer comprises a recessed sidewall that is laterally recessed outward from a vertical axis passing through a geometrical center of a volume of the memory opening and has a tapered recessed surface segment; and forming a memory opening fill structure within the memory openings, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel, and comprises a lateral protrusion having a tapered sidewall surface that is parallel to the tapered recessed surface segment.
According to an aspect of the present disclosure, a memory device is provided, which comprises: a first alternating stack of first insulating layers and first electrically conductive layers; a memory opening vertically extending through the first alternating stack; and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel, wherein the memory opening fill structure comprises a lateral protrusion having a tapered sidewall surface; and wherein one of the first electrically conductive layers comprises a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening fill structure and comprises a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.
According to another aspect of the present disclosure, a method of forming a memory device is provided, which comprises: forming a first alternating stack of first insulating layers and first sacrificial material layers located over a substrate, wherein one of the first sacrificial material layers comprises a composite sacrificial material layer including a primary sacrificial material sublayer including a first sacrificial material and a secondary sacrificial material sublayer including a second sacrificial material that is different from the first sacrificial material; forming a first-tier memory opening through the first alternating stack; performing an isotropic recess etch process that isotropically etches the second sacrificial material at a higher average etch rate than the first sacrificial material, wherein a recessed sidewall of the composite sacrificial material layer comprises a tapered recessed surface segment; and forming a memory opening fill structure within a volume including the first-tier memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel, and comprises a lateral protrusion having a tapered sidewall surface that is parallel to the tapered recessed surface segment.
Embodiments of the present disclosure provide a three-dimensional memory device including a dummy word line having a tapered corner and methods of manufacturing the same, the various aspects of which are described herein in detail. The embodiments of the present disclosure may be used to form various semiconductor devices such as three-dimensional memory array devices comprising a plurality of NAND memory strings.
The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.
The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.
As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.
As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface overlies or underlies the first surface and there exists a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from a vertical direction by an angle less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction, and may, or may not, include a curvature along a direction that is perpendicular to the vertical direction or the substantially vertical direction.
As used herein, a “memory level” or a “memory array level” refers to the level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including topmost surfaces of an array of memory elements and a second horizontal plane including bottommost surfaces of the array of memory elements. As used herein, a “through-stack” element refers to an element that vertically extends through a memory level.
As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0×105 S/m. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−5 S/m to 1.0 S/m in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/m to 1.0×107 S/m upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105 S/m. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−5 S/m. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to provide electrical conductivity greater than 1.0×105 S/m. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−5 S/m to 1.0×107 S/m. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.
Referring to
Dielectric material layers are formed over the semiconductor devices, which are herein referred to as lower-level dielectric material layers 760. The lower-level dielectric material layers 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures), first dielectric material layers 764 that overlie the dielectric liner 762, a silicon nitride layer (e.g., hydrogen diffusion barrier) 766 that overlies the first dielectric material layers 764, and at least one second dielectric layer 768.
The dielectric layer stack including the lower-level dielectric material layers 760 functions as a matrix for lower-level metal interconnect structures 780 that provide electrical wiring to and from the various nodes of the semiconductor devices and landing pads for through-memory-level contact via structures to be subsequently formed. The lower-level metal interconnect structures 780 are formed within the dielectric layer stack of the lower-level dielectric material layers 760, and comprise a lower-level metal line structure located under and optionally contacting a bottom surface of the silicon nitride layer 766.
For example, the lower-level metal interconnect structures 780 may be formed within the first dielectric material layers 764. The first dielectric material layers 764 may be a plurality of dielectric material layers in which various elements of the lower-level metal interconnect structures 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layers 764 may include any of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and dielectric metal oxides (such as aluminum oxide). In one embodiment, the first dielectric material layers 764 may comprise, or consist essentially of, dielectric material layers having dielectric constants that do not exceed the dielectric constant of undoped silicate glass (silicon oxide) of 3.9. The lower-level metal interconnect structures 780 may include various device contact via structures 782 (e.g., source and drain electrodes which contact the respective source and drain nodes of the device or gate electrode contacts), intermediate lower-level metal line structures 784, lower-level metal via structures 786, and landing-pad-level metal line structures 788 that are configured to function as landing pads for through-memory-level contact via structures to be subsequently formed.
The landing-pad-level metal line structures 788 may be formed within a topmost dielectric material layer of the first dielectric material layers 764 (which may be a plurality of dielectric material layers). Each of the lower-level metal interconnect structures 780 may include a metallic nitride liner and a metal fill structure. Top surfaces of the landing-pad-level metal line structures 788 and the topmost surface of the first dielectric material layers 764 may be planarized by a planarization process, such as chemical mechanical planarization. The silicon nitride layer 766 may be formed directly on the top surfaces of the landing-pad-level metal line structures 788 and the topmost surface of the first dielectric material layers 764.
The at least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 may include any of doped silicate glass, undoped silicate glass, and organosilicate glass. In one embodiment, the at least one first second material layer 768 may comprise, or consist essentially of, dielectric material layers having dielectric constants that do not exceed the dielectric constant of undoped silicate glass (silicon oxide) of 3.9.
An optional layer of a metallic material and a layer of a semiconductor material may be deposited over, or within patterned recesses of, the at least one second dielectric material layer 768, and is lithographically patterned to provide an optional conductive plate layer 6 and in-process source-level material layers 110′. The optional conductive plate layer 6, if present, provides a high conductivity conduction path for electrical current that flows into, or out of, the in-process source-level material layers 110′. The optional conductive plate layer 6 includes a conductive material such as a metal or a heavily doped semiconductor material. The optional conductive plate layer 6, for example, may include a tungsten layer having a thickness in a range from 3 nm to 100 nm, although lesser and greater thicknesses may also be used. A metal nitride layer (not shown) may be provided as a diffusion barrier layer on top of the conductive plate layer 6. The conductive plate layer 6 may function as a special source line in the completed device. In addition, the conductive plate layer 6 may comprise an etch stop layer and may comprise any suitable conductive, semiconductor or insulating layer. The optional conductive plate layer 6 may include a metallic compound material such as a conductive metallic nitride (e.g., TiN) and/or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in a range from 5 nm to 100 nm, although lesser and greater thicknesses may also be used.
The in-process source-level material layers 110′ may include various layers that are subsequently modified to form source-level material layers. The source-level material layers, upon formation, include a source contact layer that functions as a common source region for vertical field effect transistors of a three-dimensional memory device. In one embodiment, the in-process source-level material layers 110′ may include, from bottom to top, a lower source-level semiconductor layer 112, a lower sacrificial liner 103, a source-level sacrificial layer 104, an upper sacrificial liner 105, an upper source-level semiconductor layer 116, a source-level insulating layer 117, and an optional source-select-level conductive layer 118.
The lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be the opposite of the conductivity of vertical semiconductor channels to be subsequently formed. For example, if the vertical semiconductor channels to be subsequently formed have a doping of a first conductivity type, the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 have a doping of a second conductivity type that is the opposite of the first conductivity type. The thickness of each of the lower source-level semiconductor layer 112 and the upper source-level semiconductor layer 116 may be in a range from 10 nm to 300 nm, such as from 20 nm to 150 nm, although lesser and greater thicknesses may also be used.
The source-level sacrificial layer 104 includes a sacrificial material that may be removed selective to the lower sacrificial liner 103 and the upper sacrificial liner 105. In one embodiment, the source-level sacrificial layer 104 may include a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer 104 may be in a range from 30 nm to 400 nm, such as from 60 nm to 200 nm, although lesser and greater thicknesses may also be used.
The lower sacrificial liner 103 and the upper sacrificial liner 105 include materials that may function as an etch stop material during removal of the source-level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 may include silicon oxide, silicon nitride, and/or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 may include a silicon oxide layer having a thickness in a range from 2 nm to 30 nm, although lesser and greater thicknesses may also be used.
The source-level insulating layer 117 includes a dielectric material such as silicon oxide. The thickness of the source-level insulating layer 117 may be in a range from 20 nm to 400 nm, such as from 40 nm to 200 nm, although lesser and greater thicknesses may also be used. The optional source-select-level conductive layer 118 may include a conductive material that may be used as a source-select-level gate electrode. For example, the optional source-select-level conductive layer 118 may include a doped semiconductor material such as doped polysilicon or doped amorphous silicon that may be subsequently converted into doped polysilicon by an anneal process. The thickness of the optional source-select-level conductive layer 118 may be in a range from 30 nm to 200 nm, such as from 60 nm to 100 nm, although lesser and greater thicknesses may also be used.
The in-process source-level material layers 110′ may be formed directly above a subset of the semiconductor devices on the substrate 8 (e.g., silicon wafer). As used herein, a first element is located “directly above” a second element if the first element is located above a horizontal plane including a topmost surface of the second element and an area of the first element and an area of the second element has an areal overlap in a plan view (i.e., along a vertical plane or direction perpendicular to the top surface of the substrate 8.
The optional conductive plate layer 6 and the in-process source-level material layers 110′ may be patterned to provide openings in areas in which through-memory-level contact via structures and through-dielectric contact via structures are to be subsequently formed. Patterned portions of the stack of the conductive plate layer 6 and the in-process source-level material layers 110′ are present in each memory array region 100 in which three-dimensional memory stack structures are to be subsequently formed.
The optional conductive plate layer 6 and the in-process source-level material layers 110′ may be patterned such that an opening extends over a staircase region 200 in which contact via structures contacting word line electrically conductive layers are to be subsequently formed. In one embodiment, the staircase region 200 may be laterally spaced from the memory array region 100 along a first horizontal direction hd1. A horizontal direction that is perpendicular to the first horizontal direction hd1 is herein referred to as a second horizontal direction hd2. In one embodiment, additional openings in the optional conductive plate layer 6 and the in-process source-level material layers 110′ may be formed within the area of a memory array region 100, in which a three-dimensional memory array including memory stack structures is to be subsequently formed. A peripheral device region 400 that is subsequently filled with a field dielectric material portion may be provided adjacent to the staircase region 200.
The region of the semiconductor devices 710 and the combination of the lower-level dielectric material layers 760 and the lower-level metal interconnect structures 780 is herein referred to an underlying peripheral device region 700, which is located underneath a memory-level assembly to be subsequently formed and includes peripheral devices for the memory-level assembly. The lower-level metal interconnect structures 780 are formed in the lower-level dielectric material layers 760.
The lower-level metal interconnect structures 780 may be electrically connected to active nodes (e.g., transistor active regions 742 or gate electrodes 754) of the semiconductor devices 710 (e.g., CMOS devices), and are located at the level of the lower-level dielectric material layers 760. Through-memory-level contact via structures may be subsequently formed directly on the lower-level metal interconnect structures 780 to provide electrical connection to memory devices to be subsequently formed. In one embodiment, the pattern of the lower-level metal interconnect structures 780 may be selected such that the landing-pad-level metal line structures 788 (which are a subset of the lower-level metal interconnect structures 780 located at the topmost portion of the lower-level metal interconnect structures 780) may provide landing pad structures for the through-memory-level contact via structures to be subsequently formed.
In an alternative embodiment, the underlying peripheral device region 700, the optional conductive plate layer 6 and/or the in-process source-level material layers 110′ may be omitted. Instead, the peripheral device region 700 may be located on a separate substrate which is subsequently bonded to the memory array region 100.
Referring to
In one embodiment, the homogeneous sacrificial material layers 142H are composed of and/or consist essentially of a first sacrificial material. The composite sacrificial material layer 142C comprises a layer stack including a primary sacrificial material sublayer 142P and a secondary sacrificial material sublayer 142S. As used herein, a “sublayer” refers to a component layer of a layer that includes a contiguous set of two or more component layers (i.e., two or more sublayers). In one embodiment, the primary sacrificial material sublayer 142P comprises and/or consists essentially of, the first sacrificial material and the secondary sacrificial material sublayer 142S comprises and/or consists essentially of a second sacrificial material that has a higher etching rate than the first sacrificial material. The first sacrificial material and the second sacrificial material are materials that may be removed selective to the insulating material of the first insulating layers 132. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.
In one embodiment, the primary sacrificial material sublayer 142P underlies the secondary sacrificial material sublayer 142S. The thickness of each homogeneous sacrificial material layer 142H may be in a range from 20 nm to 60 nm, although lesser and greater thicknesses may also be employed. In one embodiment, the thickness of each homogeneous sacrificial material layer 142H may be the same. In one embodiment, the thickness of the composite sacrificial material layer 142C may be the same as, or may be substantially the same as, the thickness of each homogeneous sacrificial material layer 142H. In one embodiment, the thickness of the primary sacrificial material sublayer 142P may be in a range from 10% to 90%, such as from 25% to 75%, of the thickness of the composite sacrificial material layer 142C. In one embodiment, the thickness of the secondary sacrificial material sublayer 142S may be in a range from 10% to 90%, such as from 25% to 75%, of the thickness of the primary sacrificial material sublayer 142P.
According to an aspect of the present disclosure, the first sacrificial material and the second sacrificial material are selected such that the second sacrificial material may be removed faster than the first sacrificial material in a subsequent isotropic etch process that is selective to the insulating material of the first insulating layers 132. In one embodiment, the second sacrificial material may have a vertical compositional gradient such that the etch rate of the second sacrificial material in the subsequent anisotropic etch process decreases with a vertical distance from the substrate 8. The ratio of the average etch rate of the second sacrificial material to the etch rate of the first sacrificial material in the subsequent isotropic etch process may be in a range from 1.2 to 10, such as from 1.5 to 5, although lesser and greater ratios may also be employed. The ratio of the average etch rate of the first sacrificial material to the etch rate of the insulating material of the first insulating layers 132 in the subsequent isotropic etch process may be in a range from 2.0 to 10,000, such as from 10 to 1,000, although greater ratios may also be employed.
In an illustrative example, the first insulating layers 132 may consist essentially of silicon oxide, the homogeneous sacrificial material layers 142H and the first sacrificial material of the primary sacrificial material sublayer 142P comprise a first silicon nitride material, and the second sacrificial material of the secondary sacrificial material sublayer 142S comprises a second silicon nitride material having a higher etch rate in hot phosphoric acid than the etch rate of the first sacrificial material in the hot phosphoric acid. Hot phosphoric acid refers to phosphoric acid at or near the boiling point at 1 atmospheric pressure. In one embodiment, the primary sacrificial material sublayer 142P may consist essentially of a first silicon nitride material that is stoichiometric or near-stoichiometric (i.e., Si3N4) and/or has a relatively low density, and the secondary sacrificial material sublayer 142S may consist essentially of a second silicon nitride material that is silicon rich (i.e., Si3+xN4−x, where x>0, such as 0.1<x<1) and/or a has a lower density (e.g., at least 5% lower density, such as 7 to 15% lower density) than the first silicon nitride material. Alternatively or in addition, the second silicon nitride material may include a vertical compositional (i.e., decreasing Si:N ratio) and/or density gradient (i.e., increasing density) as a function of its thickness, such that the etch rate of the second sacrificial material in a subsequent isotropic etch process decreases with a vertical distance from the substrate 8, while the first silicon nitride material has a homogeneous composition and porosity as a function of its thickness.
Generally, the second silicon nitride material may be deposited in a condition that alters the material composition and/or porosity of silicon nitride to increase the etch rate in hot phosphoric acid by selecting deposition parameters (such as reactant ratios, pressure, temperature, plasma power, etc.) during the deposition process. In one embodiment, the first silicon nitride material and the second silicon nitride material may be deposited employing plasma-enhanced chemical vapor deposition (PECVD) processes having different process conditions.
For example, the first silicon nitride material may have a density in a range from 2.45 g/cm3 to 2.65 g/cm3. Such a low porosity silicon nitride material may be deposited by a plasma enhanced chemical vapor deposition process in which a lower plasma power is employed. In contrast, the second silicon nitride material may have a density in a range from 2.2 g/cm3 to 2.35 g/cm3. Such a relatively porous silicon nitride material may be deposited by a plasma enhanced chemical vapor deposition process in which a higher plasma power is employed. To form a density gradient as a function of thickness in the second silicon nitride material, the plasma power is decreased gradually or step-wise during the deposition of the second silicon nitride material.
A first insulating cap layer 170 is subsequently formed over the first alternating stack (132, 142). The first insulating cap layer 170 includes a dielectric material, which may be any dielectric material that may be used for the first insulating layers 132. In one embodiment, the first insulating cap layer 170 includes the same dielectric material as the first insulating layers 132. The thickness of the first insulating cap layer 170 may be in a range from 20 nm to 300 nm, although lesser and greater thicknesses may also be used.
Referring to
A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above the horizontal plane including the top surface of the first insulating cap layer 170. A remaining portion of the dielectric fill material that fills the region overlying the first stepped surfaces constitute a first retro-stepped dielectric material portion 165. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. The first alternating stack (132, 142) and the first retro-stepped dielectric material portion 165 collectively constitute a first-tier structure, which is an in-process structure that is subsequently modified.
An inter-tier dielectric layer 180 may be optionally deposited over the first-tier structure (132, 142, 170, 165). The inter-tier dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the inter-tier dielectric layer 180 may include a doped silicate glass having a greater etch rate than the material of the first insulating layers 132 (which may include an undoped silicate glass). For example, the inter-tier dielectric layer 180 may include phosphosilicate glass. The thickness of the inter-tier dielectric layer 180 may be in a range from 30 nm to 300 nm, although lesser and greater thicknesses may also be used.
Referring to
The first-tier memory openings 149 are openings that are formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form memory stack structures therein. The first-tier memory openings 149 may be formed in clusters of first-tier memory openings 149 that are laterally spaced apart along the second horizontal direction hd2. Each cluster of first-tier memory openings 149 may be formed as a two-dimensional array of first-tier memory openings 149.
The first-tier support openings 129 are openings that are formed in the staircase region 200, and are subsequently employed to form support pillar structures. A subset of the first-tier support openings 129 that is formed through the first retro-stepped dielectric material portion 165 may be formed through a respective horizontal surface of the first stepped surfaces.
In one embodiment, the first anisotropic etch process may include an initial step in which the materials of the first alternating stack (132, 142) are etched concurrently with the material of the first retro-stepped dielectric material portion 165. The chemistry of the initial etch step may alternate to optimize etching of the materials in the first alternating stack (132, 142) while providing a comparable average etch rate to the material of the first retro-stepped dielectric material portion 165. The first anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reaction etch process (e.g., CF4/O2/Ar etch). The sidewalls of the various first-tier openings (149, 129) may be substantially vertical, or may be tapered.
After etching through the alternating stack (132, 142) and the first retro-stepped dielectric material portion 165, the chemistry of a terminal portion of the first anisotropic etch process may be selected to etch through the dielectric material(s) of the at least one second dielectric layer 768 with a higher etch rate than an average etch rate for the in-process source-level material layers 110′. For example, the terminal portion of the anisotropic etch process may include a step that etches the dielectric material(s) of the at least one second dielectric layer 768 selective to a semiconductor material within a component layer in the in-process source-level material layers 110′. In one embodiment, the terminal portion of the first anisotropic etch process may etch through the source-select-level conductive layer 118, the source-level insulating layer 117, the upper source-level semiconductor layer 116, the upper sacrificial liner 105, the source-level sacrificial layer 104, and the lower sacrificial liner 103, and at least partly into the lower source-level semiconductor layer 112. The terminal portion of the first anisotropic etch process may include at least one etch chemistry for etching the various semiconductor materials of the in-process source-level material layers 110′. The photoresist layer may be subsequently removed, for example, by ashing.
Optionally, the portions of the first-tier memory openings 149 and the first-tier support openings 129 at the level of the inter-tier dielectric layer 180 may be laterally expanded by an isotropic etch. In this case, the inter-tier dielectric layer 180 may comprise a dielectric material (such as borosilicate glass) having a greater etch rate than the first insulating layers 132 (that may include undoped silicate glass) in dilute hydrofluoric acid. An isotropic etch (such as a wet etch using HF) may be used to expand the lateral dimensions of the first-tier memory openings 149 at the level of the inter-tier dielectric layer 180. The portions of the first-tier memory openings 149 located at the level of the inter-tier dielectric layer 180 may be optionally widened to provide a larger landing pad for second-tier memory openings to be subsequently formed through a second alternating stack (to be subsequently formed prior to formation of the second-tier memory openings).
Referring to
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In an illustrative example, the second sacrificial material may have a lower density and/or a vertical compositional gradient and/or density gradient to provide a higher etch rate than the first sacrificial material. In this case, the isotropic recess etch process may comprise a wet etch process employing hot phosphoric acid, or hydrofluoric acid, or a mixture of hydrofluoric acid and ethylene glycol.
The composite sacrificial material layer 142C is patterned into a taper-containing sacrificial material layer comprising a contoured sidewall having a tapered sidewall segment. In one embodiment, the recessed sidewall of the composite sacrificial material layer 142C may comprise a tapered recessed surface segment, which may be a tapered annular surface segment of the secondary sacrificial material sublayer 142S. The tapered annular surface segment can have an inner periphery that is vertically offset from an outer periphery by a vertical offset distance and laterally offset from the outer periphery by a lateral offset distance. Further, the recessed sidewall of the composite sacrificial material layer 142C may comprise a cylindrical vertical surface segment that is adjoined to the tapered recessed surface segment. The cylindrical vertical surface segment may be a recessed sidewall segment of the primary sacrificial material sublayer 142P. In one embodiment, the vertical offset distance may be in a range from 10% to 90% of a vertical thickness of the taper-containing sacrificial material layer.
Each first-tier memory opening 149 comprises a tapered annular recess 149T located at the level of the composite sacrificial material layer 142C and cylindrical annular recesses 149C located at the levels of the homogeneous sacrificial material layers 142H.
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The thicknesses of the second insulating layers 232 and the second sacrificial material layers 242 may be in a range from 20 nm to 50 nm, although lesser and greater thicknesses may be used for each second insulating layer 232 and for each second sacrificial material layer 242. The number of repetitions of the pairs of a second insulating layer 232 and a second sacrificial material layer 242 may be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions may also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) may have a uniform thickness that is substantially invariant within each respective second sacrificial material layer 242.
Second stepped surfaces in the second stepped area may be formed in the staircase region 200 using a same set of processing steps as the processing steps used to form the first stepped surfaces in the first stepped area with suitable adjustment to the pattern of at least one masking layer. A second retro-stepped dielectric material portion 265 may be formed over the second stepped surfaces in the staircase region 200.
A second insulating cap layer 270 may be subsequently formed over the second alternating stack (232, 242). The second insulating cap layer 270 includes a dielectric material that is different from the material of the second sacrificial material layers 242. In one embodiment, the second insulating cap layer 270 may include silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) may comprise silicon nitride.
Generally speaking, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) may be formed over the in-process source-level material layers 110′, and at least one retro-stepped dielectric material portion (165, 265) may be formed over the staircase regions on the at least one alternating stack (132, 142, 232, 242).
Optionally, drain-select-level isolation structures 72 may be formed through a subset of layers in an upper portion of the second alternating stack (232, 242). The second sacrificial material layers 242 that are cut by the drain-select-level isolation structures 72 correspond to the levels in which drain-select-level electrically conductive layers are subsequently formed. The drain-select-level isolation structures 72 include a dielectric material such as silicon oxide. The drain-select-level isolation structures 72 may laterally extend along a first horizontal direction hd1, and may be laterally spaced apart along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The combination of the second alternating stack (232, 242), the second retro-stepped dielectric material portion 265, the second insulating cap layer 270, and the optional drain-select-level isolation structures 72 collectively constitute a second-tier structure (232, 242, 265, 270, 72).
Referring to
The pattern of openings in the photoresist layer may be transferred through the second-tier structure (232, 242, 265, 270, 72) by a second anisotropic etch process to form various second-tier openings (249, 229) concurrently, i.e., during the second anisotropic etch process. The various second-tier openings (249, 229) may include second-tier memory openings 249 and second-tier support openings 229.
The second-tier memory openings 249 are formed directly on a top surface of a respective one of the sacrificial first-tier memory opening fill portions 148. The second-tier support openings 229 are formed directly on a top surface of a respective one of the sacrificial first-tier support opening fill portions 128. Further, each second-tier support openings 229 may be formed through a horizontal surface within the second stepped surfaces, which include the interfacial surfaces between the second alternating stack (232, 242) and the second retro-stepped dielectric material portion 265. Locations of steps S in the first alternating stack (132, 142) and the second alternating stack (232, 242) are illustrated as dotted lines in
The second anisotropic etch process may include an etch step in which the materials of the second alternating stack (232, 242) are etched concurrently with the material of the second retro-stepped dielectric material portion 265. The chemistry of the etch step may alternate to optimize etching of the materials in the second alternating stack (232, 242) while providing a comparable average etch rate to the material of the second retro-stepped dielectric material portion 265. The second anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reaction etch process (e.g., CF4/O2/Ar etch). The sidewalls of the various second-tier openings (249, 229) may be substantially vertical, or may be tapered. A bottom periphery of each second-tier opening (249, 229) may be laterally offset, and/or may be located entirely within, a periphery of a top surface of an underlying sacrificial first-tier opening fill portion (148, 128). The photoresist layer may be subsequently removed, for example, by ashing.
Referring to
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Subsequently, the charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers (142, 242). In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layers (142, 242) and the insulating layers (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layers (142, 242) may be laterally recessed with respect to the sidewalls of the insulating layers (132, 232), and a combination of a deposition process and an anisotropic etch process may be used to form the charge storage layer 54 as a plurality of memory material portions that are vertically spaced apart. The thickness of the charge storage layer 54 may be in a range from 2 nm to 20 nm, although lesser and greater thicknesses may also be used.
The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling may be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer 56 may be in a range from 2 nm to 20 nm, although lesser and greater thicknesses may also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.
The semiconductor channel material layer 60L includes a p-doped semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may having a uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping in which p-type dopants (such as boron atoms) are present at an atomic concentration in a range from 1.0×1012/cm3 to 1.0×1018/cm3, such as from 1.0×1014/cm3 to 1.0×1017/cm3. In one embodiment, the semiconductor channel material layer 60L includes, and/or consists essentially of, boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping in which n-type dopants (such as phosphor atoms or arsenic atoms) are present at an atomic concentration in a range from 1.0×1012/cm3 to 1.0×1018/cm3, such as from 1.0×1014/cm3 to 1.0×1017/cm3. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in a range from 2 nm to 10 nm, although lesser and greater thicknesses may also be used. A cavity 49′ is formed in the volume of each memory opening 49 that is not filled with the deposited material layers (52, 54, 56, 60L). A cavity 49′ may be present in the volume that is not filled with the various deposited material layers (50, 60L) in each memory opening 49.
Referring to
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Each remaining portion of the doped semiconductor material of the second conductivity type constitutes a drain region 63. The dopant concentration in the drain regions 63 may be in a range from 5.0×1019/cm3 to 2.0×1021/cm3, although lesser and greater dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.
Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60 through which electrical current may flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a charge storage layer 54, and laterally surrounds a vertical semiconductor channel 60. Each adjoining set of a blocking dielectric layer 52, a charge storage layer 54, and a tunneling dielectric layer 56 collectively constitute a memory film 50, which may store electrical charges with a macroscopic retention time. In some embodiments, a blocking dielectric layer 52 may not be present in the memory film 50 at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.
Each combination of a memory film 50 and a vertical semiconductor channel 60 within a memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a vertical semiconductor channel 60, a tunneling dielectric layer 56, a plurality of memory elements comprising portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of a memory stack structure 55, a dielectric core 62, and a drain region 63 within a memory opening 49 constitutes a memory opening fill structure 58. The in-process source-level material layers 110′, the first-tier structure (132, 142, 170, 165), the second-tier structure (232, 242, 270, 265, 72), the inter-tier dielectric layer 180, the memory opening fill structures 58, and support pillar structures that are formed in the support openings 19 collectively constitute a memory-level assembly.
Generally, each memory opening fill structure 58 can be formed within a volume including a first-tier memory opening 149 and a second-tier memory opening 249 (in case a second alternating stack is employed). Each memory opening fill structure 58 comprises a memory film 50 including a tunneling dielectric layer 56, a vertical stack of memory elements such as portions of the charge storage layer 54 located at the levels of the sacrificial material layers (142, 242), and a blocking dielectric layer 52. According to an aspect of the present disclosure, each memory opening fill structure 58 comprises a tapered lateral protrusion 58T having a tapered outer sidewall surface 58S located at the level of the composite sacrificial material layer 142C. A portion of an outer sidewall of the memory film 50 that vertically extends through the first alternating stack (132, 142) has a contoured vertical cross-sectional profile in which segments 50A of the outer sidewall of the memory film 50 located at levels of the first sacrificial material layers 142 laterally protrude farther outward from a vertical axis VA passing through a geometrical center GC of the memory opening fill structure 58 than segments 50B of the outer sidewall of the memory film 50 contacting sidewalls of the first insulating layers 132. In one embodiment, the entirety of a volume of the lateral protrusions 58P of the memory opening fill structure 58 at the levels of the first sacrificial material layers 142 may be filled with the memory film 50. The outer sidewall of the tapered lateral protrusion 58T may extend further away from the vertical axis VA than the outer sidewalls of the lateral protrusions 58P.
In one embodiment, a second alternating stack of second insulating layers 232 and second sacrificial material layers 242 may overlie the first alternating stack (132, 142). Each memory opening fill structure 58 may vertically extend through the second alternating stack (232, 242). In one embodiment, a portion of the outer sidewall of the memory film 50 in each memory opening fill structure 58 can vertically extend through the second alternating stack (232, 242), and can have a straight vertical cross-sectional profile that extends from a bottommost layer within the second alternating stack (232, 242) to a topmost layer within the alternating stack (232, 242). Thus, the memory opening fill structure 58 may lack the lateral protrusions 58P at the levels of the second alternating stack (232, 242).
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Wet etch chemicals such as hot TMY and TMAH are selective to doped semiconductor materials such as the p-doped semiconductor material and/or the n-doped semiconductor material of the upper source-level semiconductor layer 116 and the lower source-level semiconductor layer 112. Thus, use of selective wet etch chemicals such as hot TMY and TMAH for the wet etch process that forms the source cavity 109 provides a large process window against etch depth variation during formation of the backside trenches 79. Specifically, even if sidewalls of the upper source-level semiconductor layer 116 are physically exposed or even if a surface of the lower source-level semiconductor layer 112 is physically exposed upon formation of the source cavity 109 and/or the backside trench spacers 77, collateral etching of the upper source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 is minimal, and the structural change to the first exemplary structure caused by accidental physical exposure of the surfaces of the upper source-level semiconductor layer 116 and/or the lower source-level semiconductor layer 112 during manufacturing steps do not result in device failures. Each of the memory opening fill structures 58 is physically exposed to the source cavity 109. Specifically, each of the memory opening fill structures 58 includes a sidewall and that are physically exposed to the source cavity 109.
Referring to
Referring to
In one embodiment, the doped semiconductor material of the second conductivity type may be deposited on the physically exposed semiconductor surfaces around the source cavity 109 by a selective semiconductor deposition process. A semiconductor precursor gas, an etchant, and a dopant gas may be flowed concurrently into a process chamber including the first exemplary structure during the selective semiconductor deposition process. For example, the semiconductor precursor gas may include silane, disilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include a hydride of a dopant atom such as phosphine, arsine, stibine, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material having a doping of the second conductivity type from physically exposed semiconductor surfaces around the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114, which may contact sidewalls of the vertical semiconductor channels 60. The atomic concentration of the dopants of the second conductivity type in the deposited semiconductor material may be in a range from 1.0×1020/cm3 to 2.0×1021/cm3, such as from 2.0×1020/cm3 to 8.0×1020/cm3. The source contact layer 114 as initially formed may consist essentially of semiconductor atoms and dopant atoms of the second conductivity type. Alternatively, at least one non-selective doped semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch back processes may be used in combination with a plurality of selective or non-selective deposition processes to provide a seamless and/or voidless source contact layer 114.
The duration of the selective semiconductor deposition process may be selected such that the source cavity 109 is filled with the source contact layer 114, and the source contact layer 114 contacts bottom end portions of inner sidewalls of the backside trench spacers 77. In one embodiment, the source contact layer 114 may be formed by selectively depositing a doped semiconductor material having a doping of the second conductivity type from semiconductor surfaces around the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Thus, the source-level sacrificial layer 104 may be replaced with the source contact layer 114.
The layer stack including the lower source-level semiconductor layer 112, the source contact layer 114, and the upper source-level semiconductor layer 116 constitutes a buried source layer (112, 114, 116). The set of layers including the buried source layer (112, 114, 116), the source-level insulating layer 117, and the source-select-level conductive layer 118 constitutes source-level material layers 110, which replaces the in-process source-level material layers 110′.
Referring to
An oxidation process may be performed to convert physically exposed surface portions of semiconductor materials into dielectric semiconductor oxide portions. For example, surfaces portions of the source contact layer 114 and the upper source-level semiconductor layer 116 may be converted into dielectric semiconductor oxide plates 122, and surface portions of the source-select-level conductive layer 118 may be converted into annular dielectric semiconductor oxide spacers 124.
Referring to
The isotropic etch process may be a wet etch process using a wet etch solution, or may be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trench 79. For example, if the sacrificial material layers (142, 242) include silicon nitride, the etch process may be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials used in the art.
Backside recesses (143, 243) are formed in volumes from which the sacrificial material layers (142, 242) are removed. The backside recesses (143, 243) include first backside recesses 143 that are formed in volumes from which the first sacrificial material layers 142 are removed and second backside recesses 243 that are formed in volumes from which the second sacrificial material layers 242 are removed. Each of the backside recesses (143, 243) may be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) may be greater than the height of the respective backside recess (143, 243). A plurality of backside recesses (143, 243) may be formed in the volumes from which the material of the sacrificial material layers (142, 242) is removed. Each of the backside recesses (143, 243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. A backside recess (143, 243) may be vertically bounded by a top surface of an underlying insulating layer (132, 232) and a bottom surface of an overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) may have a uniform height throughout.
Referring to
At least one conductive material may be deposited in the plurality of backside recesses (143, 243), on the sidewalls of the backside trenches 79, and over the first contact-level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.
In one embodiment, the at least one conductive material may include at least one metallic material, i.e., an electrically conductive material that includes at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recesses (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metallic nitride liner that includes a conductive metallic nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or combinations thereof. In one embodiment, the at least one conductive material for filling the backside recesses (143, 243) may be a combination of titanium nitride layer and a tungsten fill material.
Electrically conductive layers (146, 246) may be formed in the backside recesses (143, 243) by deposition of the at least one conductive material. A plurality of first electrically conductive layers 146 may be formed in the plurality of first backside recesses 143, a plurality of second electrically conductive layers 246 may be formed in the plurality of second backside recesses 243, and a continuous metallic material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact-level dielectric layer 280. Each of the first electrically conductive layers 146 and the second electrically conductive layers 246 may include a respective conductive metallic nitride liner and a respective conductive fill material. Thus, the first and second sacrificial material layers (142, 242) may be replaced with the first and second electrically conductive layers (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer 44 and a first electrically conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer 44 and a second electrically conductive layer 246. A backside cavity is present in the portion of each backside trench 79 that is not filled with the continuous metallic material layer.
Residual conductive material may be removed from inside the backside trenches 79. Specifically, the deposited metallic material of the continuous metallic material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact-level dielectric layer 280, for example, by an anisotropic or isotropic etch. Each remaining portion of the deposited metallic material in the first backside recesses constitutes a first electrically conductive layer 146. Each remaining portion of the deposited metallic material in the second backside recesses constitutes a second electrically conductive layer 246. Sidewalls of the first electrically conductive material layers 146 and the second electrically conductive layers may be physically exposed to a respective backside trench 79. The backside trenches may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.
Each electrically conductive layer (146, 246) may be a conductive sheet including openings therein. A first subset of the openings through each electrically conductive layer (146, 246) may be filled with memory opening fill structures 58. A second subset of the openings through each electrically conductive layer (146, 246) may be filled with the support pillar structures 20. Each electrically conductive layer (146, 246) may have a lesser area than any underlying electrically conductive layer (146, 246) because of the first and second stepped surfaces. Each electrically conductive layer (146, 246) may have a greater area than any overlying electrically conductive layer (146, 246) because of the first and second stepped surfaces.
Each of the memory stack structures 55 comprises a vertical stack of memory elements located at each level of the electrically conductive layers (146, 246). A subset of the electrically conductive layers (146, 246) may comprise word lines for the memory elements. The semiconductor devices in the underlying peripheral device region 700 may comprise word line switch devices configured to control a bias voltage to respective word lines. The memory-level assembly is located over the substrate semiconductor layer 9. The memory-level assembly includes at least one alternating stack (132, 146, 232, 246) and memory stack structures 55 vertically extending through the at least one alternating stack (132, 146, 232, 246).
In some embodiments, drain-select-level isolation structures 72 may be provided at topmost levels of the second electrically conductive layers 246. A subset 246D of the second electrically conductive layers 246 located at the levels of the drain-select-level isolation structures 72 constitutes drain select gate electrodes. A subset (146W, 246W) of the electrically conductive layers (146, 246) located underneath the drain select gate electrodes constitutes word lines which may function as combinations of a control gate and a word line located at the same level. The control gate electrodes (146W, 246W) within each electrically conductive layer (146, 246) are the control gate electrodes for a vertical memory device including the memory stack structure 55. A subset 146E of the first electrically conductive layers 146 located below the word lines (146W, 246W) constitutes source select gate electrodes.
Generally, the first sacrificial material layers 142 can be replaced with the first electrically conductive layers 146. One of the first electrically conductive layers 146 comprises a taper-containing electrically conductive layer 146T that is formed in a volume from which the composite sacrificial material layer 142C is removed. The taper-containing electrically conductive layer 146T is located at the level of the tapered lateral protrusion 58T of a respective memory opening fill structure 58 located in a respective memory opening 49. The taper-containing electrically conductive layer 146T may function as a dummy word line. In other words, the dummy word line is not used to program or read a memory cell, but is activated to maintain current flow through the vertical semiconductor channel 60 at the joint region between the first and second alternating stacks.
In one embodiment shown in
In one embodiment, the inner periphery of the annular tapered sidewall segment is adjoined to a first closed periphery of a first horizontal surface of the taper-containing electrically conductive layer 146T, and the outer periphery of the annular tapered sidewall segment is adjoined to a second closed periphery of a second horizontal surface of the taper-containing electrically conductive layer 146T. In one embodiment, the inner periphery of the tapered sidewall segment may be laterally offset outward from a cylindrical sidewall of a first insulating layer 132 that is most proximal to the taper-containing electrically conductive layer 146T of the first insulating layers 132 by a uniform lateral offset distance “lod”. In one embodiment, each of the first electrically conductive layers 146 except the taper-containing electrically conductive layer 146T comprises a respective cylindrical sidewall that is laterally offset from a respective most proximal underlying first insulating layer 132 of the first insulating layers 132 by the uniform lateral offset distance “lod”.
In one embodiment shown in
A second alternating stack of second insulating layers 232 and second electrically conductive layers 246 can overlie the first alternating stack (132, 146). The memory opening fill structure 58 vertically extends through the second alternating stack (232, 246). A portion of the outer sidewall of the memory film 50 of each memory opening fill structure 58 can vertically extend through the second alternating stack (232, 246), and can have a straight vertical cross-sectional profile that extends from a bottommost layer within the second alternating stack (232, 246) to a topmost layer within the alternating stack (232, 246).
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Drain contact via structures 88 are formed in the drain contact via cavities and on a top surface of a respective one of the drain regions 63. Staircase-region contact via structures 86 are formed in the staircase-region contact via cavities and on a top surface of a respective one of the electrically conductive layers (146, 246). The staircase-region contact via structures 86 may include drain select level contact via structures that contact a subset of the second electrically conductive layers 246 that function as drain select level gate electrodes. Further, the staircase-region contact via structures 86 may include word line contact via structures that contact electrically conductive layers (146, 246) that underlie the drain select level gate electrodes and function as word lines for the memory stack structures 55.
Referring to
At least one additional dielectric layer may be formed over the contact-level dielectric layers (280, 282), and additional metal interconnect structures (herein referred to as upper-level metal interconnect structures) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line-level dielectric layer 290 that is formed over the contact-level dielectric layers (280, 282). The upper-level metal interconnect structures may include bit lines 98 contacting a respective one of the drain contact via structures 88, and interconnection line structures 96 contacting, and/or electrically connected to, at least one of the staircase-region contact via structures 86 and/or the peripheral-region contact via structures 488. The word line contact via structures (which are provided as a subset of the staircase-region contact via structures 86) may be electrically connected to the word line driver circuit through a subset of the lower-level metal interconnect structures 780 and through a subset of the peripheral-region contact via structures 488.
In one embodiment, the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device, the electrically conductive strips (146, 246) comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device, the substrate 8 comprises a silicon substrate, the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate, and at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings. The silicon substrate may contain an integrated circuit comprising a driver circuit for the memory device located thereon, the electrically conductive strips (146, 246) comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate 8, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level. The array of monolithic three-dimensional NAND strings comprises a plurality of semiconductor channels 60, wherein at least one end portion of each of the plurality of semiconductor channels 60 extends substantially perpendicular to a top surface of the substrate 8, and one of the plurality of semiconductor channels including the vertical semiconductor channel 60. The array of monolithic three-dimensional NAND strings comprises a plurality of charge storage elements (comprising portions of the memory films 50), each charge storage element located adjacent to a respective one of the plurality of semiconductor channels 60.
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The composite sacrificial material layer 142C is patterned into a taper-containing sacrificial material layer comprising a contoured sidewall having a tapered sidewall segment. In one embodiment, the recessed sidewall of the composite sacrificial material layer 142C may comprise a tapered recessed surface segment. Specifically, a surface segment of the primary sacrificial material sublayer 142P that is adjoined to a cylindrical recessed vertical sidewall of the secondary sacrificial material sublayer 142S may comprise the tapered recessed sidewall segment, which can be a tapered annular surface segment. The tapered annular surface segment can have an inner periphery that is vertically offset from an outer periphery by a vertical offset distance and laterally offset from the outer periphery by a lateral offset distance. Further, the recessed sidewall of the composite sacrificial material layer 142C may comprise a first cylindrical vertical surface segment that is adjoined to the inner periphery of the tapered recessed surface segment, and a second cylindrical vertical surface segment that is adjoined to the outer periphery of the tapered recessed surface segment. The first cylindrical vertical surface segment may be a recessed sidewall segment of the primary sacrificial material sublayer 142P, and the second cylindrical vertical surface segment may be a recessed sidewall segment of the secondary sacrificial material layer 142S. In one embodiment, the vertical offset distance may be in a range from 10% to 50% of a vertical thickness of the taper-containing sacrificial material layer.
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Referring to all drawings and according to various embodiments of the present disclosure, a memory device is provided, which comprises: a first alternating stack of first insulating layers 132 and first electrically conductive layers 146; a memory opening 49 vertically extending through the first alternating stack (132, 146); and a memory opening fill structure 58 located in the memory opening 49 and comprising a vertical stack of memory elements and a vertical semiconductor channel 60. The memory opening fill structure 58 comprises a lateral protrusion 58T having a tapered sidewall surface 58S. One of the first electrically conductive layers 146 comprises a taper-containing electrically conductive layer 146T that is located at a level of the lateral protrusion 58T of the memory opening fill structure 58 and comprises a contoured sidewall having a tapered sidewall segment 146S that is parallel to the tapered sidewall surface 58S of the lateral protrusion 58T.
In one embodiment, the taper-containing electrically conductive layer 146T comprises a dummy word line. In one embodiment, the tapered sidewall segment 146S is an annular tapered sidewall segment having an inner periphery that is vertically offset from an outer periphery by a vertical offset distance. In one embodiment, the vertical offset distance is in a range from 10% to 100% of a vertical thickness of the taper-containing electrically conductive layer 146T. In one embodiment, the inner periphery of the annular tapered sidewall segment 146S is adjoined to a first closed periphery of a first horizontal surface of the taper-containing electrically conductive layer 146T; and the outer periphery of the annular tapered sidewall segment 146S is adjoined to a second closed periphery of a second horizontal surface of the taper-containing electrically conductive layer 146T.
In one embodiment shown in
In one embodiment, the inner periphery of the tapered sidewall segment 146S is laterally offset outward from a cylindrical sidewall of a first insulating layer that is most proximal to the taper-containing electrically conductive layer 146T of the first insulating layers 132 by a uniform lateral offset distance lod. In one embodiment, each of the first electrically conductive layers 146 except the taper-containing electrically conductive layer 146T comprises a respective vertical cylindrical sidewall that is laterally offset from a respective most proximal underlying first insulating layer 132 of the first insulating layers 132 by the uniform lateral offset distance lod.
In one embodiment, the memory opening fill structure 58 comprises a memory film 50 including a tunneling dielectric layer 56, the vertical stack of memory elements (as embodied as portions of a charge storage layer 54 located at the levels of the electrically conductive layers (146, 246), and a blocking dielectric layer 52; and an entirety of a volume of the lateral protrusion of the memory opening fill structure 58 is filled with the memory film 50.
In one embodiment, the memory device further comprises a source layer (112, 114, 116) located between the substrate 8 and the first alternating stack (132, 146) and contacting a bottom end of the memory film 50 and contacting the vertical semiconductor channel 60.
In one embodiment, a portion of an outer sidewall of the memory film that vertically extends through the first alternating stack (132, 146) has a contoured vertical cross-sectional profile in which segments of the outer sidewall of the memory film 50 located at levels of the first electrically conductive layers 146 laterally protrude farther outward from a vertical axis VA passing through a geometrical center GC of the memory opening fill structure 58 than segments of the outer sidewall of the memory film 50 contacting sidewalls of the first insulating layers 132.
In one embodiment, memory device comprises a second alternating stack of second insulating layers 232 and second electrically conductive layers 246 overlying the first alternating stack (132, 146), wherein the memory opening fill structure 58 vertically extends through the second alternating stack (232, 246).
In one embodiment, a portion of the outer sidewall of the memory film 50 that vertically extends through the second alternating stack (232, 246) has a straight vertical cross-sectional profile that extends from a bottommost layer within the second alternating stack (232, 246) to a topmost layer within the alternating stack (232, 246).
In one embodiment, the dummy word line 146T is located adjacent to a joint region between the first alternating stack and the second alternating stack.
The electric field at the vertical channel 60 facing edge of the taper-containing dummy word line 146T is reduced due to the presence of the tapered sidewall segment 146S. The reduced electric field reduces back tunneling and provides an improved deep erase depth. Thus, the starting erase voltage for back tunneling is increased and the device erase efficiency is improved by forming the taper-containing dummy word line 146T.
Referring to
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The composite sacrificial material layer 242C comprises a layer stack including, from bottom to top, a secondary sacrificial material layer 242S and a primary sacrificial material sublayer 242P. The primary sacrificial material sublayer 242P in the second exemplary structure can have the same material composition and the same thickness range as the primary sacrificial material layer 142P in the first exemplary structure. The secondary sacrificial material sublayer 242S in the second exemplary structure can have the same material composition and the same thickness range as the secondary sacrificial material layer 142S in the first exemplary structure.
Generally, the homogeneous sacrificial material layers 242 and the primary sacrificial material layer 242P within the composite sacrificial material layer 242C may be composed of a first sacrificial material, and the secondary sacrificial material layer 242S within the composite sacrificial material layer 242C may be composed of a second sacrificial material different from the first sacrificial material. As in the first exemplary structure, the first sacrificial material and the second sacrificial material in the second exemplary structure are selected such that the second sacrificial material may be removed faster than the first sacrificial material in a subsequent isotropic etch process that is selective to the insulating material of the first insulating layers 132.
Alternatively, the primary sacrificial material layer 242P may comprise a third sacrificial material which is different from the first and the second sacrificial materials. The third sacrificial material may have a higher etch rate than the first sacrificial material and a lower etch rate than the second sacrificial material.
In one embodiment, the second sacrificial material may have a vertical compositional gradient such that the etch rate of the second sacrificial material in the subsequent anisotropic etch process decreases with a vertical distance from the substrate 8. The ratio of the average etch rate of the second sacrificial material to the etch rate of the first sacrificial material in the subsequent isotropic etch process may be in a range from 1.2 to 10, such as from 1.5 to 5, although lesser and greater ratios may also be employed. The ratio of the average etch rate of the first sacrificial material to the etch rate of the insulating material of the first insulating layers 132 in the subsequent isotropic etch process may be in a range from 2.0 to 10,000, such as from 10 to 1,000, although greater ratios may also be employed.
In an illustrative example, the first insulating layers 132 and the second insulating layers 232 may consist essentially of silicon oxide, the homogeneous sacrificial material layers 242H and the first sacrificial material of the primary sacrificial material sublayer 242P comprise a first silicon nitride material, and the second sacrificial material of the secondary sacrificial material sublayer 242S comprises a second silicon nitride material having a higher etch rate in hot phosphoric acid than the etch rate of the first sacrificial material in the hot phosphoric acid. In one embodiment, the primary sacrificial material sublayer 242P may consist essentially of a first silicon nitride material that is stoichiometric or near-stoichiometric (i.e., Si3N4) and/or has a relatively low density, and the secondary sacrificial material sublayer 242S may consist essentially of a second silicon nitride material that is silicon rich (i.e., Si3+xN4−x, where x>0, such as 0.1<x<1) and/or a has a lower density (e.g., at least 5% lower density, such as 7 to 15% lower density) than the first silicon nitride material. Alternatively or in addition, the second silicon nitride material may include a vertical compositional (i.e., increasing Si:N ratio) and/or density gradient (i.e., decreasing density) as a function of its thickness, such that the etch rate of the second sacrificial material in a subsequent isotropic etch process decreases with a vertical distance from the substrate 8, while the first silicon nitride material has a homogeneous composition and porosity as a function of its thickness.
Referring collectively to the first exemplary structure and the second exemplary structure, at least one alternating stack {(132, 142), (232, 242)} can be formed over a substrate 8. Each of the at least one alternating stack {(132, 142), (232, 242)} comprises respective insulating layers (132, 232) and respective sacrificial material layers (142, 242) that are interlaced along a vertical direction. One of the sacrificial material layers (142, 242) of the at least one alternating stack {(132, 142), (232, 242)} comprises a composite sacrificial material layer (142C or 242C) including a primary sacrificial material sublayer (142P or 242P) including a first sacrificial material and a secondary sacrificial material sublayer (142S or 242S) including a second sacrificial material that is different from the first sacrificial material. In one embodiment, the at least one alternating stack {(132, 142), (232, 242)} comprises: a first alternating stack (132, 142) of first insulating layers 132 and first sacrificial material layers (142, 242); and a second alternating stack (232, 242) of second insulating layers 232 and second sacrificial material layers (142, 242) that overlies the first alternating stack (132, 142). In one embodiment, an inter-tier dielectric layer 180 can be located between the first alternating stack (132, 142) and the second alternating stack (232, 242). The memory opening fill structures 58 may comprise a respective laterally protruding portion having a top surface located within a horizontal plane including a top surface of the inter-tier dielectric layer 180. In one embodiment, the composite sacrificial material layer (142C or 242C) may comprise a topmost first sacrificial material layer 142 and/or a bottommost second sacrificial material layer 242, and may be subsequently replaced with a respective dummy word line.
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Generally, each memory opening 49 can be formed through the at least one alternating stack {(132, 142), (232, 242)} such that the composite sacrificial material layer (142C or 242C) comprises a respective recessed sidewall that is laterally recessed outward from a vertical axis VA passing through a geometrical center GC of a volume of the respective memory opening 49, and has a respective tapered recessed surface segment. Each recessed sidewall of the composite sacrificial material layer (142C or 242C) comprises a respective cylindrical vertical surface segment that is adjoined to the respective tapered recessed surface segment. In one embodiment, the recessed sidewall of the composite sacrificial material layer (142C or 242C) is formed by performing an isotropic recess etch process that isotropically etches the second sacrificial material at a higher average etch rate than the first sacrificial material.
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Generally, each memory opening fill structure 58 can be formed within a volume including a first-tier memory opening 149 and a second-tier memory opening 249 (in case a second alternating stack is employed). Each memory opening fill structure 58 comprises a memory film 50 including a tunneling dielectric layer 56, a vertical stack of memory elements such as portions of the charge storage layer 54 located at the levels of the sacrificial material layers (142, 242), and a blocking dielectric layer 52. According to an aspect of the present disclosure, each memory opening fill structure 58 comprises a tapered lateral protrusion 58T having a tapered outer sidewall surface 58S located at the level of the composite sacrificial material layer 242C.
In one embodiment, a portion of an outer sidewall of the memory film 50 that vertically extends through the at least one alternating stack {(132, 142), (232, 242)} has a contoured vertical cross-sectional profile in which segments of the outer sidewall of the memory film 50 located at levels of the sacrificial material layers (142, 242) of the at least one alternating stack {(132, 142), (232, 242)} laterally protrude farther outward from a vertical axis VA passing through a geometrical center GC of the memory opening fill structure 58 than segments of the outer sidewall of the memory film 50 contacting sidewalls of the insulating layers (132, 232) of the at least one alternating stack {(132, 142), (232, 242)}. In one embodiment, a portion of an outer sidewall of the memory film 50 that vertically extends through the second alternating stack (132, 142) has a contoured vertical cross-sectional profile in which segments 501 of the outer sidewall of the memory film 50 located at levels of the second sacrificial material layers 242 laterally protrude farther outward from a vertical axis VA passing through a geometrical center GC of the memory opening fill structure 58 than segments 502 of the outer sidewall of the memory film 50 contacting sidewalls of the second insulating layers 232.
Additional lateral protrusions 58Q may be provided at each level of the second sacrificial material layers 242 that overlie the composite sacrificial material layer 242T. In one embodiment, the entirety of each volume of the lateral protrusions 58Q of each memory opening fill structure 58 at the levels of the first sacrificial material layers 142 may be filled with a portion of a respective memory film 50. The outer sidewall of the tapered lateral protrusion 58T may extend further away from the vertical axis VA than the outer sidewalls of the additional lateral protrusions 58Q.
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Referring collectively to the first exemplary structure and the second exemplary structure, the sacrificial material layers (142, 242) of the at least one alternating stack {(132, 142), (232, 242)} can be replaced with electrically conductive layers (146, 246). At least one of the electrically conductive layers (146, 246) comprises a taper-containing electrically conductive layer (146T and/or 246T) that is formed in a volume from which the composite sacrificial material layer (142T and/or 242T) is removed. In one embodiment, the taper-containing electrically conductive layer (146T and/or 246T) comprises a dummy word line having a contoured sidewall having a tapered sidewall segment (146S and/or 246S) that is parallel to the tapered sidewall surface 58S of the lateral protrusion.
In one embodiment, the memory device includes two taper-containing electrically conductive layers (146T and 246T). In this embodiment, the first tier (i.e., the lower tier) includes the first taper-containing electrically conductive layer 146T as the topmost electrically conductive layer, while the second tier (i.e., the upper tier) includes the second taper-containing electrically conductive layer 246T as the bottommost electrically conductive layer. The tapers of the first and the second taper-containing electrically conductive layers extend in opposite directions relative to the vertical distance from the substrate 8.
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Referring to all drawings and according to various embodiments of the present disclosure, a memory device comprises at least one alternating stack {(132, 146), (232, 246)} of insulating layers (132, 232) and electrically conductive layers (146, 246); a memory opening 49 vertically extending through the at least one alternating stack {(132, 146), (232, 246)}; and a memory opening fill structure 58 located in the memory opening 49 and comprising a vertical stack of memory elements (which may comprise portions of a charge storage layer 54 located at levels of the electrically conductive layers (146, 246)) and a vertical semiconductor channel 60. The memory opening fill structure 58 comprises a lateral protrusion having a tapered sidewall surface 58S; and one of the electrically conductive layers (146, 246) of the at least one alternating stack {(132, 146), (232, 246)} comprises a taper-containing electrically conductive layer (146T or 246T) that is located at a level of the lateral protrusion of the memory opening fill structure 58.
In one embodiment, the taper-containing electrically conductive layer 246T comprises a dummy word line. In one embodiment, the taper-containing electrically conductive layer 246T comprises a contoured sidewall having a tapered sidewall segment 246S that is parallel to the tapered sidewall surface 58S of the lateral protrusion. In one embodiment, the tapered sidewall segment 246S is an annular tapered sidewall segment 246S having an inner periphery that is vertically offset from an outer periphery by a vertical offset distance.
In one embodiment, the vertical offset distance is in a range from 10% to 100% of a vertical thickness of the taper-containing electrically conductive layer 246T; and the inner periphery of the annular tapered sidewall segment 246S is adjoined to a first closed periphery of a first horizontal surface of the taper-containing electrically conductive layer 246T; and the outer periphery of the annular tapered sidewall segment 246S is adjoined to a second closed periphery of a second horizontal surface of the taper-containing electrically conductive layer 246T.
In one embodiment, the contoured sidewall comprises a first vertical straight cylindrical sidewall segment that is adjoined to the outer periphery of the annular tapered sidewall segment 246S. In one embodiment, the contoured sidewall further comprises a second vertical straight cylindrical sidewall segment that is adjoined to the inner periphery of the annular tapered sidewall segment 246S. In one embodiment, the inner periphery of the annular tapered sidewall segment 246S is adjoined to a closed periphery of a horizontal surface of the taper-containing electrically conductive layer 246T.
In one embodiment, the inner periphery of the tapered sidewall segment 246S is laterally offset outward from a cylindrical sidewall of one of the insulating layers 232 that is most proximal to the taper-containing electrically conductive layer 246T by a uniform lateral offset distance. In one embodiment, each of the electrically conductive layers (146, 246) except the taper-containing electrically conductive layer 246T comprises a respective vertical cylindrical sidewall that is laterally offset from a respective most proximal underlying one of the first insulating layers 132 by the uniform lateral offset distance.
In one embodiment, the memory opening fill structure 58 comprises a memory film 50 including a tunneling dielectric layer 56, the vertical stack of memory elements (which may be embodied as portions of a charge storage layer 54 located at levels of the electrically conductive layers (146, 246)), and a blocking dielectric layer 52; and an entirety of a volume of the lateral protrusion of the memory opening fill structure 58 is filled with the memory film 50.
In one embodiment, a portion of an outer sidewall of the memory film 50 that vertically extends through the at least one alternating stack {(132, 146), (232, 246)} has a contoured vertical cross-sectional profile in which segments of the outer sidewall of the memory film 50 located at levels of the electrically conductive layers (146, 246) of the at least one alternating stack {(132, 146), (232, 246)} laterally protrude farther outward from a vertical axis passing through a geometrical center of the memory opening fill structure 58 than segments of the outer sidewall of the memory film 50 contacting sidewalls of the insulating layers (132, 232) of the at least one alternating stack {(132, 146), (232, 246)}.
In one embodiment, the at least one alternating stack {(132, 146), (232, 246)} comprises: a first alternating stack (132, 146) of first insulating layers 132 and first electrically conductive layers (146, 246); and a second alternating stack (232, 246) of second insulating layers 232 and second electrically conductive layers (146, 246) that overlies the first alternating stack (132, 146). In one embodiment, the taper-containing electrically conductive layer 246T is a bottommost second electrically conductive layer (146, 246).
In one embodiment, the memory device comprises an inter-tier dielectric layer 180 located between the first alternating stack (132, 146) and the second alternating stack (232, 246), wherein the memory opening fill structure 58 comprises a laterally protruding portion having a top surface located within a horizontal plane including a top surface of the inter-tier dielectric layer 180.
The electric field at the vertical channel 60 facing edge of the taper-containing dummy word line (146T and/or 246T) is reduced due to the presence of the tapered sidewall segment (146S and/or 246S). The reduced electric field reduces back tunneling and provides an improved deep erase depth. Thus, the starting erase voltage for back tunneling is increased and the device erase efficiency is improved by forming the taper-containing dummy word line (146T and/or 246T).
Although the foregoing refers to particular embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment using a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17715662 | Apr 2022 | US |
| Child | 18060732 | US |
