Patent Application
20240322775
A power combiner is a device that may be configured to combine the power from multiple sources into a single output. To that end, a power combiner includes two or more branches, each branch including a transmission line for transmitting signals to be combined, where transmission lines of different branches are coupled to respective signal sources at one end and coupled together to a single output at the other end. Such a device may also be operated in reverse, where the ends of the transmission lines of different branches that are coupled together are coupled to a single input and the other ends of the transmission lines of different branches are coupled to respective outputs. In this manner, the device may also be used to divide an incoming signal into multiple paths and may be referred to as a “power divider.” Because a single device may be configured to operate either as a power combiner or a power divider, depending on the configuration of the inputs and outputs of the device, the term “power combiner” may be used to refer to both power combiners and power dividers.
Power combiners may be used in wireless communication devices, such as handheld computing devices and wireless access points. A power combiner configured to combine multiple input signals into a single output may be used in a transmit (TX) path of a wireless communication device to combine outputs of multiple power amplifiers (PAs) into a single output that may be provided to an antenna. A power combiner configured to divide a single input signal into multiple outputs may be used in a receive (RX) path of a wireless communication device to divide a signal generated by an antenna into multiple outputs for further processing, e.g., for further processing by respective low-noise amplifiers (LNAs) associated with different branches of a power combiner.
Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings.
The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.
For purposes of illustrating IC packages with 3D power combiners, proposed herein, it might be useful to first understand phenomena that may come into play in some systems where power combiners may be used. The following foundational information may be viewed as a basis from which the present disclosure may be properly explained. Such information is offered for purposes of explanation only and, accordingly, should not be construed in any way to limit the broad scope of the present disclosure and its potential applications.
One class of systems where power combiners may be used are wireless communication systems that transmit and receive signals in the form of electromagnetic waves in the RF range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz) and beyond. In context of a wireless communication system, an antenna is a device that serves as the interface between electromagnetic waves propagating wirelessly through space and electric currents moving in metal conductors used with a transmitter or a receiver of a wireless communication device. During transmission, a transmitter supplies an electric current to the antenna's terminals, and the antenna radiates the energy from the current as electromagnetic waves. During reception, an antenna intercepts some of the power of an electromagnetic wave in order to produce an electric current at its terminals, which current is subsequently applied to a receiver to be amplified.
Antennas are essential components of all wireless communication devices. An antenna with a single antenna unit will typically broadcast a radiation pattern that radiates in all directions in a spherical wavefront. Phased arrays generally refer to a collection of antenna units that are used to focus electromagnetic energy in a particular direction, thereby creating a main beam. Phased arrays offer numerous advantages over single antenna systems, such as high gain, ability to perform directional steering, and simultaneous communication, and, therefore, are particularly important for modern wireless communication systems.
As the frequency of operation of wireless communication devices increased into the millimeter wave, sub-Terahertz (THz), and THz regions, the output power of semiconductor devices used in the transceivers decreases substantially. In order to increase the overall strength of the transmitted signal, an on-chip power combiner may be used between the last amplification stage and an antenna unit or an antenna port. Even though the wavelength is small at such frequencies, a multi-branch power combiner occupies a significant area, therefore, leading to die size and cost increase. This problem is further exacerbated for wireless communication devices employing phased arrays, where a respective power combiner may need to be provided for each of the antenna units.
Disclosed herein are electronic assemblies, IC packages, and communication devices that may enable wireless communications such as millimeter wave and THz communications in a compact form factor by implementing three-dimensional power combiners. Such assemblies, packages, and devices may include a plurality of dies stacked above one another, where individual dies include respective transmission lines that may be configured to serve as different branches of a power combiner. By stacking the dies above one another different branches of a power combiner may be provided in different planes, thus realizing a three-dimensional power combiner. The three-dimensional integration may enable compactness and form factor reduction. In some embodiments, adjacent dies of the stack may be coupled to one another using direct bonding interconnects (also referred to as “hybrid bonding interconnects”), which may advantageously lead to reduced impedance discontinuity at high frequencies. In some embodiments, the overall utilization of dies may be improved by re-orienting the circuits on the floor plan of the dies.
As an example, an electronic assembly according to some embodiments of the present disclosure may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. Each of the dies includes a first face and an opposing second face, and each of the transmission lines has a first end and an opposing second end. The second die may be stacked above the first die so that the first face of the second die is coupled to the second face of the first die. The electronic assembly may further include a first conductive pathway between the first end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between the first end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the second end of the first transmission line and the second end of the second transmission line. The first and second transmission lines of such an electronic assembly may form different branches of a power combiner. Because the first and second transmission lines are provided in dies stacked above one another, such a power combiner may be referred to as a “three-dimensional power combiner,” to differentiate it from conventional power combiners where different branches are provided in a single plane (e.g., on a single die).
In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.
Any of the features discussed with reference to any of accompanying drawings herein may be combined with any other features to form a power combiner arrangement 100, an electronic assembly 130, an IC package 140, or a communication device, as appropriate. A number of elements of the drawings are shared with others of the drawings; for ease of discussion, a description of these elements is not repeated, and these elements may take the form of any of the embodiments disclosed herein. Also for convenience, the phrase “dies 104” may be used to refer to the collection of dies 104-1, 104-2, and so on, the phrase “transmission lines 106” may be used to refer to the collection of transmission lines 106-1, 106-2, and so on, etc. To not clutter the drawings, if multiple instances of certain elements are illustrated, only some of the elements may be labeled with a reference sign. The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration and may not reflect real-life process limitations which may cause various features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electro microscopy (SEM) images or transmission electro microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using, e.g., Physical Failure Analysis (PFA) would allow determination of presence of three-dimensional power combiners as described herein.
Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y. When used to describe a location of an element, the phrase “between X and Y” represents a region that is spatially between element X and element Y. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−20%, e.g., within +/−5% or within +/−2%, of a target value based on the context of a particular value as described herein or as known in the art.
The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Furthermore, the terms “chip,” “chiplet,” “die,” and “IC die” may be used interchangeably herein.
Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “a dielectric material” may include one or more dielectric materials. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. The term “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, while the term “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. The term “insulating” and variations thereof (e.g., “insulative” or “insulator”) means “electrically insulating,” the term “conducting” and variations thereof (e.g., “conductive” or “conductor”) means “electrically conducting,” unless otherwise specified. With reference to optical signals and/or devices, components and elements that operate on or using optical signals, the term “conducting” can also mean “optically conducting.” The term “insulating material” refers to solid materials (and/or liquid materials that solidify after processing as described herein) that are substantially electrically nonconducting. They may include, as examples and not as limitations, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon and alumina or a combination thereof. They may include dielectric materials, high polarizability materials, and/or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are underfills and molds or mold-like materials used in packaging applications, including for example, materials used in organic interposers, package supports and other such components. The term “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via).
The term “package substrate” may be used to describe any substrate material that facilitates the packaging together of any collection of semiconductor dies and/or other electrical components such as passive electrical components. As used herein, a package substrate may be formed of any material including, but not limited to, insulating materials such as resin impregnated glass fibers (e.g., printed circuit board (PCB) or Printed Wiring Boards (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate that includes buildup layers (e.g., ABF layers). In some embodiments, a package substrate may be a PCB or a multilayer package substrate that includes a core including glass, e.g., a core including a glass layer, where the glass layer may be bulk glass or a solid volume of glass, as opposed to, e.g., glass fiber reinforced polymers (i.e., in some embodiments, the glass layer does not include any glass fiber reinforced polymers).
In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “lines,” “wires,” “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, electrically conductive traces and vias may be referred to as “conductive traces” and “conductive vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PCI. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.
The term “metallization stack” may be used to refer to a stack of one or more interconnects for providing connectivity to different circuit components of an IC die/chip and/or a package substrate. The term “conductive trace” may be used to describe an electrically conductive element isolated by an insulating material. Within IC dies, such insulating material comprises interlayer low-k dielectric that is provided within the IC die. Within package substrates, and PCBs such insulating material may comprise organic materials such as Ajinomoto Buildup Film (ABF), polyimides, or epoxy resin. Such conductive lines are typically arranged in several levels, or several layers, of metallization stacks. The term “conductive via” may be used to describe an electrically conductive element that interconnects two or more conductive lines of different levels of a metallization stack. To that end, a via may be provided substantially perpendicularly to the plane of an IC die/chip or a support structure over which an IC structure is provided and may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.
As shown in
Each of the transmission lines 106 may include a first end 107-1 and an opposing second end 107-2. A conductive pathway 110-1 may be between (i.e., electrically connecting, e.g., directly connecting) the first end 107-1 of the first transmission line 106-1 and a first connection point 112-2 at the first face 108-1 of the first die 104-1. A conductive pathway 110-2 may be between the first end 107-1 of the second transmission line 106-2 and a second connection point 112-2 at the first face 108-1 of the first die 104-1. More generally, if more than two dies 104 with transmission lines 106 are included in the power combiner arrangement 100 (e.g., as discussed below with reference to
The direct bonding interconnect 120 shown in the inset 111 may be one of a plurality of direct bonding interconnects 120 coupling the first die 104-1 and the second die 104-2, with an insulator material 124 also being present between the first die 104-1 and the second die 104-2 and surrounding the direct bonding interconnects 120. Coupling various dies 104 stacked above one another using direct bonding interconnects 120 may advantageously allow reducing impedance discontinuity in the power combiner arrangement 100. Furthermore, direct bonding interconnects 120 may allow decreasing the distance between adjacent dies 104 stacked above one another, compared to, e.g., solder-based interconnects. For example, in some embodiments, the first and second dies 104-1, 104-2 may be separated by distance 126 that may be below about 10 microns, e.g., below about 5 microns or below about 2 microns, e.g., between about 0.5 microns and 2 microns.
As used herein, “direct bonding” (also sometimes referred to as “hybrid bonding”) refers to bonding of two dies 104 without using solder-based interconnects. In some embodiments, bonding of the opposite faces of a pair of IC dies 104 may be performed using insulator-insulator bonding, e.g., as oxide-oxide bonding, where an insulator material of one die 104 is bonded to an insulator material of the another die 104, resulting in the insulator material 124 being present at a direct bonding interface between the dies 104. To that end, in some embodiments, an insulator material may be applied to the one or both faces of the first and second dies 104 that should be bonded and then the dies 104 are pressed together, possibly while applying a suitable pressure and heating up the assembly to a suitable temperature (e.g., to moderately high temperatures, e.g., between about 50 and 130 degrees Celsius) for a duration of time. In some embodiments, the insulator material 124 may include an adhesive material that ensures attachment of the first and second dies 104 to one another. In some embodiments, the insulator material 124 may include an etch-stop material. In some embodiments, the insulator material 124 may be both an etch-stop material and have suitable adhesive properties to ensure attachment of the first and second dies 104 to one another. In some embodiments, the insulator material 124 may include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, e.g., between about 1% and 50%, indicating that these elements are added deliberately, as opposed to being accidental impurities which are typically in concentration below about 0.1%. Having both nitrogen and carbon in these concentrations in addition to silicon is not typically used in conventional semiconductor manufacturing processes where, typically, either nitrogen or carbon is used in combination with silicon, and, therefore, could be a characteristic feature of the direct bonding where different dies 104 may be manufactured by different manufacturers or using different fabrication processes. Using an etch-stop material at the interface (i.e., the interface between the first and second dies 104) that includes include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, e.g., SiOCN, may be advantageous in terms that such a material may act both as an etch-stop material, and have sufficient adhesive properties to bond the first and second dies 104 together. In addition, an etch-stop material at the interface between the first and second dies 104 that includes include silicon, nitrogen, and carbon, where the atomic percentage of any of these materials may be at least 1%, may be advantageous in terms of improving etch selectivity of this material with respect to etch-stop materials that may be used in different of the first and second dies 104. In some embodiments, no deliberately added adhesive or bonding material may be used to bond the first and second dies 104, but there will still be a direct bonding interface in the form of the insulator material 124 resulting from the bonding of the first and second dies 104 to one another. Such a direct bonding interface may be recognizable as a seam or a thin layer in the electronic assembly, using, e.g., selective area diffraction (SED), even when the specific materials of the insulators of the first and second dies 104 that are bonded together may be the same, in which case the direct bonding interface would still be noticeable as a seam or a thin layer in what otherwise appears as a bulk insulator (e.g., bulk oxide) layer.
The circuits 132 may include any suitable circuitry for controlling how the electromagnetic waves are transmitted and received. In some embodiments, any of the circuits 132 may include a termination resistor that is electrically coupled to two branches of the power combiner. In some embodiments, if the power combiner arrangement 100 is used to combine multiple input signals into a single output, then the circuits 132 may include PAs (e.g., each of the circuits 132 may include a respective power amplifier). On the other hand, if the power combiner arrangement 100 is used to divide a single input signal into multiple outputs, then the circuits 132 may include LNAs (e.g., each of the circuits 132 may include a respective LNA). In some embodiments, each of the circuits 132 may include both a power amplifier and an LNA, so that the power combiner arrangement 100 coupled to the die 102 may be configured to operate either to combine multiple input signals into a single output or to divide a single input signal into multiple outputs, as needed. In some such embodiments, an electronic assembly 130 may include a switch configured to select whether the power combiner arrangement 100 is to operate to combine multiple input signals into a single output or to operate to divide a single input signal into multiple outputs. In other embodiments, an electronic assembly 130 may include separate power combiner arrangements 100 for combining multiple input signals into a single output and dividing a single input signal into multiple outputs. For example,
The power combiner arrangement 100 and the electronic assembly 130 may be included in any suitable IC package. For example,
The components 136 may include any suitable IC components that may include a three-dimensional power combiner arrangement 100, possibly as a part of an electronic assembly 200. In some embodiments, one or more of the components 136 may include a die. For example, one or more of the components 136 may be a RF communication die such as the die 102, coupled to one or more power combiner arrangements 100, as described with reference to an electronic assembly 200. In various embodiments, the die 102 and the one or more power combiner arrangements 100 may be arranged in various manners with respect to one another and the package substrate 134. For example, in some embodiments, any of the components 136 may include a die 102 and a power combiner arrangement 100 arranged so that the die 102 is closer to the package substrate 134 than the power combiner arrangement 100 (e.g., the die 102 may be coupled between the power combiner arrangement 100 and the package substrate 134). However, in other embodiments, any of the components 136 may include a die 102 and a power combiner arrangement 100 arranged so that the power combiner arrangement 100 is closer to the package substrate 134 than the die 102 (e.g., the power combiner arrangement 100 may be coupled between the die 102 and the package substrate 134). In some embodiments, one or more of the components 136 may include a resistor, capacitor (e.g., decoupling capacitors), inductor, DC-DC converter circuitry, or other circuit elements. In some embodiments, the IC package 140 may be a system-in-package (SiP). In some embodiments, the IC package 140 may be a flip chip (FC) chip scale package (CSP). In some embodiments, one or more of the components 136 may include a memory device programmed with instructions to execute beam forming, scanning, and/or codebook functions.
In some embodiments, a package substrate 134 of an IC package 140 in a power combiner arrangement 100 may include one or more recesses. For example,
In some embodiments, the interconnects 166 may be first-level interconnects, e.g., similar to the first-level interconnects 150, described above. In other embodiments, the interconnects 166 may be second-level interconnects, e.g., similar to the second-level interconnects 142, described above. Conductive contacts 162, 164 may be similar to any other conductive contacts described herein, e.g., similar to the conductive contacts 144, 146, or 148, described above.
Although not specifically shown in
In some embodiments, the interconnects 176 or the interconnects 186 may be first-level interconnects, e.g., similar to the first-level interconnects 150, described above. In other embodiments, the interconnects 176 or the interconnects 186 may be second-level interconnects, e.g., similar to the second-level interconnects 142, described above. Conductive contacts 174, 184 may be similar to any other conductive contacts described herein, e.g., similar to the conductive contacts 144, 146, or 148, described above.
Although not specifically shown in
Together, the die 102, the antenna substrate 160, and the one or more power combiner arrangements 100 coupled therebetween may constitute an antenna module 180. In some embodiments, multiple such antenna modules 180 may be coupled to a single component 178, as illustrated in
In some embodiments, an IC package 140 with one or more power combiner arrangements 100 may include one or more arrays of antenna units 192 to support multiple communication bands (e.g., dual band operation or tri-band operation). For example, some of the IC packages 140 disclosed herein may support tri-band operation at 28 gigahertz, 39 gigahertz, and 60 gigahertz. Various ones of the IC packages 140 disclosed herein may support tri-band operation at 24.5 gigahertz to 29 gigahertz, 37 gigahertz to 43 gigahertz, and 57 gigahertz to 71 gigahertz. Various ones of the IC packages 140 disclosed herein may support 5G communications and 60 gigahertz communications. Various ones of the IC packages 140 disclosed herein may support 28 gigahertz and 39 gigahertz communications. Various ones of the IC packages 140 disclosed herein may support operation in bands above about 100 gigahertz, above about 200 gigahertz, or above about 300 gigahertz. Various of the IC packages 140 disclosed herein may support millimeter wave or THz wave communications. Various of the IC packages 140 disclosed herein may support high band frequencies and low band frequencies.
In some embodiments, an antenna substrate 160 may include an antenna unit 192 coupled to an antenna support 190 by an adhesive.
The circuit board 194 may include traces, vias, and other structures, as known in the art, formed of an electrically conductive material (e.g., a metal, such as copper). The conductive structures in the circuit board 194 may be electrically insulated from each other by a dielectric material. Any suitable dielectric material may be used (e.g., a laminate material). In some embodiments, the dielectric material may be an organic dielectric material, a fire retardant grade 4 material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics).
In the embodiment of
In some embodiments, an antenna substrate 160 may include an antenna unit 192 coupled to an antenna support 190 by solder.
Any suitable antenna structures may provide the antenna units 192 of an IC package 140. In some embodiments, an antenna unit 192 may include one, two, three, or more antenna layers. For example,
The power combiner arrangements 100 disclosed herein may be included in any suitable communication device (e.g., a computing device with wireless communication capability, a wearable device with wireless communication circuitry, etc.). For example,
The three-dimensional power combiner arrangements 100 disclosed herein may include, or be included in, any suitable electronic component.
The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and/or drain (S/D) regions 1620, a gate 1622 to control current flow in the transistors 1640 between the S/D regions 1620, and one or more S/D contacts 1624 to route electrical signals to/from the S/D regions 1620. The transistors 1640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1640 are not limited to the type and configuration depicted in
Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1620 may be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S/D regions 1620 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate 1602 to form the S/D regions 1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S/D regions 1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1620. In some implementations, the S/D regions 1620 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1620 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1620.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors 1640) of the device layer 1604 through one or more interconnect layers disposed on the device layer 1604 (illustrated in
The interconnect structures 1628 may be arranged within the interconnect layers 1606-1610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1628 depicted in
In some embodiments, the interconnect structures 1628 may include lines 1628a and/or vias 1628b filled with an electrically conductive material such as a metal. The lines 1628a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1602 upon which the device layer 1604 is formed. For example, the lines 1628a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 1606-1610 may include a dielectric material 1626 disposed between the interconnect structures 1628, as shown in
A first interconnect layer 1606 may be formed above the device layer 1604. In some embodiments, the first interconnect layer 1606 may include lines 1628a and/or vias 1628b, as shown. The lines 1628a of the first interconnect layer 1606 may be coupled with contacts (e.g., the S/D contacts 1624) of the device layer 1604.
A second interconnect layer 1608 may be formed above the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b to couple the lines 1628a of the second interconnect layer 1608 with the lines 1628a of the first interconnect layer 1606. Although the lines 1628a and the vias 1628b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1608) for the sake of clarity, the lines 1628a and the vias 1628b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
A third interconnect layer 1610 (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1608 according to similar techniques and configurations described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1619 in the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.
The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606-1610. In
The IC device assembly 1700 includes a number of components disposed on a circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first face 1740 of the circuit board 1702 and an opposing second face 1742 of the circuit board 1702; generally, components may be disposed on one or both faces 1740 and 1742.
In some embodiments, the circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate.
The IC device assembly 1700 illustrated in
The package-on-interposer structure 1736 may include an IC package 1720 coupled to an interposer 1704 by coupling components 1718. The coupling components 1718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1716. Although a single IC package 1720 is shown in
In some embodiments, the interposer 1704 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including but not limited to through-silicon vias (TSVs) 1706. The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, PAs, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 1700 may include an IC package 1724 coupled to the first face 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with reference to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with reference to the IC package 1720.
The IC device assembly 1700 illustrated in
Additionally, in various embodiments, the communication device 1800 may not include one or more of the components illustrated in
The communication device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The communication device 1800 may include a memory 1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
In some embodiments, the communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, the communication module 1812 may be configured for managing wireless communications for the transfer of data to and from the communication device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication module 1812 may be, or may include, any of the power combiner arrangements 100 disclosed herein.
The communication module 1812 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication module 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication module 1812 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication module 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication module 1812 may operate in accordance with other wireless protocols in other embodiments. The communication device 1800 may include an antenna 1822 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication module 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication module 1812 may include multiple communication modules. For instance, a first communication module 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication module 1812 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication module 1812 may be dedicated to wireless communications, and a second communication module 1812 may be dedicated to wired communications. In some embodiments, the communication module 1812 may include a power combiner arrangement 100 that supports millimeter wave communication.
The communication device 1800 may include battery/power circuitry 1814. The battery/power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the communication device 1800 to an energy source separate from the communication device 1800 (e.g., AC line power).
The communication device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The communication device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The communication device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). The audio input device 1824 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The communication device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and may receive a location of the communication device 1800, as known in the art.
The communication device 1800 may include an other output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The communication device 1800 may include an other input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The communication device 1800 may have any desired form factor, such as a handheld or mobile communication device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop communication device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable communication device. In some embodiments, the communication device 1800 may be any other electronic device that processes data.
In general, the RF device 2500 may be any device or system that may support wireless transmission and/or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz) and beyond. In some embodiments, the RF device 2500 may be used for wireless communications, e.g., in a base station (BS) or a user equipment (UE) device of any suitable cellular wireless communications technology, such as GSM, WCDMA, or LTE. In a further example, the RF device 2500 may be used as, or in, a BS or a UE device of a millimeter wave wireless technology such as fifth generation (5G) wireless (e.g., high-frequency/short wavelength spectrum, with frequencies in the range between about 20 and 60 GHz, corresponding to wavelengths in the range between about 5 and 15 millimeters). In yet another example, the RF device 2500 may be used for wireless communications using Wi-Fi technology (e.g., a frequency band of 2.4 GHz, corresponding to a wavelength of about 12 cm, or a frequency band of 5.8 GHz, corresponding to a wavelength of about 5 cm). For example, the RF device 2500 may be included in a Wi-Fi-enabled device such as a desktop, a laptop, a video game console, a smart phone, a tablet, a smart TV, a digital audio player, a car, a printer, etc. In some implementations, a Wi-Fi-enabled device may be a node (e.g., a smart sensor) in a smart system configured to communicate data with other nodes. In another example, the RF device 2500 may be used for wireless communications using Bluetooth technology (e.g., a frequency band from about 2.4 to about 2.485 GHz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF device 2500 may be used for transmitting and/or receiving RF signals for purposes other than communication (e.g., in an automotive radar system, or in medical applications such as magnetic resonance imaging (MRI)).
In various embodiments, the RF device 2500 may be included in frequency-division duplex (FDD) or time-domain duplex (TDD) variants of frequency allocations that may be used in a cellular network. In an FDD system, the uplink (i.e., RF signals transmitted from the UE devices to a BS) and the downlink (i.e., RF signals transmitted from the BS to the US devices) may use separate frequency bands at the same time. In a TDD system, the uplink and the downlink may use the same frequencies but at different times.
A number of components are illustrated in
In some embodiments, some or all of the components included in the RF device 2500 may be attached to one or more motherboards. In various embodiments, the RF device 2500 may not include one or more of the components illustrated in
As shown in
The antenna 2502 may be configured to wirelessly transmit and/or receive RF signals in accordance with any wireless standards or protocols, e.g., Wi-Fi, LTE, or GSM, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. If the RF device 2500 is an FDD transceiver, the antenna 2502 may be configured for concurrent reception and transmission of communication signals in separate, e.g., non-overlapping and non-continuous, bands of frequencies, e.g., in bands having a separation of, e.g., 20 MHz from one another. If the RF device 2500 is a TDD transceiver, the antenna 2502 may be configured for sequential reception and transmission of communication signals in bands of frequencies that may be the same or overlapping for TX and RX paths. In some embodiments, the RF device 2500 may be a multi-band RF device, in which case the antenna 2502 may be configured for concurrent reception of signals having multiple RF components in separate frequency bands and/or configured for concurrent transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna 2502 may be a single wide-band antenna or a plurality of band-specific antennas (e.g., a plurality of antennas each configured to receive and/or transmit signals in a specific band of frequencies). In various embodiments, the antenna 2502 may include a plurality of antenna elements, e.g., a plurality of antenna elements forming a phased antenna array (i.e., a communication system or an array of antennas that may use a plurality of antenna elements and phase shifting to transmit and receive RF signals). Compared to a single-antenna system, a phased antenna array may offer advantages such as increased gain, ability of directional steering, and simultaneous communication. In some embodiments, the RF device 2500 may include more than one antenna 2502 to implement antenna diversity. In some such embodiments, the RF switch 2534 may be deployed to switch between different antennas.
An output of the antenna 2502 may be coupled to the input of the duplexer 2504. The duplexer 2504 may be any suitable component configured for filtering multiple signals to allow for bidirectional communication over a single path between the duplexer 2504 and the antenna 2502. The duplexer 2504 may be configured for providing RX signals to the RX path of the RF device 2500 and for receiving TX signals from the TX path of the RF device 2500.
The RF device 2500 may include one or more local oscillators 2506, configured to provide local oscillator signals that may be used for downconversion of the RF signals received by the antenna 2502 and/or upconversion of the signals to be transmitted by the antenna 2502.
The RF device 2500 may include the digital processing unit 2508, which may include one or more processing devices. In some embodiments, the digital processing unit 2508 may be implemented as the processing device 1802 of
Turning to the details of the RX path that may be included in the RF device 2500, the RX path amplifier 2512 may include an LNA. An input of the RX path amplifier 2512 may be coupled to an antenna port (not shown) of the antenna 2502, e.g., via the duplexer 2504. The RX path amplifier 2512 may amplify the RF signals received by the antenna 2502.
An output of the RX path amplifier 2512 may be coupled to an input of the RX path pre-mix filter 2514, which may be a harmonic or band-pass (e.g., low-pass) filter, configured to filter received RF signals that have been amplified by the RX path amplifier 2512.
An output of the RX path pre-mix filter 2514 may be coupled to an input of the RX path mixer 2516, also referred to as a downconverter. The RX path mixer 2516 may include two inputs and one output. A first input may be configured to receive the RX signals, which may be current signals, indicative of the signals received by the antenna 2502 (e.g., the first input may receive the output of the RX path pre-mix filter 2514). A second input may be configured to receive local oscillator signals from one of the local oscillators 2506. The RX path mixer 2516 may then mix the signals received at its two inputs to generate a downconverted RX signal, provided at an output of the RX path mixer 2516. As used herein, downconversion refers to a process of mixing a received RF signal with a local oscillator signal to generate a signal of a lower frequency. In particular, the RX path mixer (e.g., downconverter) 2516 may be configured to generate the sum and/or the difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device 2500 may implement a direct-conversion receiver (DCR), also known as homodyne, synchrodyne, or zero-intermediate frequency (IF) receiver, in which case the RX path mixer 2516 may be configured to demodulate the incoming radio signals using local oscillator signals whose frequency is identical to, or very close to the carrier frequency of the radio signal. In other embodiments, the RF device 2500 may make use of downconversion to an IF. IFs may be used in superheterodyne radio receivers, in which a received RF signal is shifted to an IF, before the final detection of the information in the received signal is done. Conversion to an IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and to tune. In some embodiments, the RX path mixer 2516 may include several such stages of IF conversion.
Although a single RX path mixer 2516 is shown in the RX path of
The output of the RX path mixer 2516 may, optionally, be coupled to the RX path post-mix filter 2518, which may be low-pass filters. In case the RX path mixer 2516 is a quadrature mixer that implements the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers respectively may be coupled to respective individual first and second RX path post-mix filters included in the RX path post-mix filter 2518.
The ADC 2520 may be configured to convert the mixed RX signals from the RX path mixer 2516 from the analog to the digital domain. The ADC 2520 may be a quadrature ADC that, similar to the RX path mixer 2516, may include two ADCs, configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC 2520 may be provided to the digital processing unit 2508, configured to perform various functions related to digital processing of the RX signals so that information encoded in the RX signals can be extracted.
Turning to the details of the TX path that may be included in the RF device 2500, the digital signal to later be transmitted (TX signal) by the antenna 2502 may be provided, from the digital processing unit 2508, to the DAC 2530. Similar to the ADC 2520, the DAC 2530 may include two DACs, configured to convert, respectively, digital I- and Q-path TX signal components to analog form.
Optionally, the output of the DAC 2530 may be coupled to the TX path pre-mix filter 2528, which may be a band-pass (e.g., low-pass) filter (or a pair of band-pass, e.g., low-pass, filters, in case of quadrature processing) configured to filter out, from the analog TX signals output by the DAC 2530, the signal components outside of the desired band. The digital TX signals may then be provided to the TX path mixer 2526, which may also be referred to as an upconverter. Similar to the RX path mixer 2516, the TX path mixer 2526 may include a pair of TX path mixers, for in-phase and quadrature component mixing. Similar to the first and second RX path mixers that may be included in the RX path, each of the TX path mixers of the TX path mixer 2526 may include two inputs and one output. A first input may receive the TX signal components, converted to the analog form by the respective DAC 2530, which are to be upconverted to generate RF signals to be transmitted. The first TX path mixer may generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2530 with the in-phase component of the TX path local oscillator signal provided from the local oscillator 2506 (in various embodiments, the local oscillator 2506 may include a plurality of different local oscillators, or be configured to provide different local oscillator frequencies for the RX path mixer 2516 in the RX path and the TX path mixer 2526 in the TX path). The second TX path mixer may generate a quadrature phase (Q) upconverted signal by mixing the TX signal component converted to analog form by the DAC 2530 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer may be added to the output of the first TX path mixer to create a real RF signal. A second input of each of the TX path mixers may be coupled the local oscillator 2506.
Optionally, the RF device 2500 may include the TX path post-mix filter 2524, configured to filter the output of the TX path mixer 2526.
As noted above, the TX path amplifier 2522 may be a power amplifier, configured to amplify the upconverted RF signal before providing it to the antenna 2502 for transmission.
In various embodiments, any of the RX path pre-mix filter 2514, the RX path post-mix filter 2518, the TX path post-mix filter 2524, and the TX path pre-mix filter 2528 may be implemented as RF filters. In some embodiments, each of such RF filters may include one or more resonators (e.g., AWRs, film bulk acoustic resonators (FBARs), Lamb wave resonators, and/or contour-wave resonators), arranged in any suitable manner (e.g., in a ladder configuration). In some embodiments, an RF filter may be implemented as a plurality of RF filters, or a filter bank. A filter bank may include a plurality of RF resonators that may be coupled to a switch (e. g., the RF switch 2534) configured to selectively switch any one of the plurality of RF resonators on and off (e.g., activate any one of the plurality of RF resonators), in order to achieve desired filtering characteristics of the filter bank (e.g., in order to program the filter bank). For example, such a filter bank may be used to switch between different RF frequency ranges when the RF device 2500 is, or is included in, a BS or in a UE device. In another example, such a filter bank may be programmable to suppress TX leakage on the different duplex distances.
The impedance tuner 2532 may include any suitable circuitry, configured to match the input and output impedances of the different RF circuitries to minimize signal losses in the RF device 2500. For example, the impedance tuner 2532 may include an antenna impedance tuner. Being able to tune the impedance of the antenna 2502 may be particularly advantageous because antenna's impedance is a function of the environment that the RF device 2500 is in, e.g., antenna's impedance changes depending on, e.g., if the antenna is held in a hand, placed on a car roof, etc.
As described above, the RF switch 2534 may be a device configured to route high-frequency signals through transmission paths in order to selectively switch between a plurality of instances of any one of the components shown in
The RF device 2500 provides a simplified version and, in further embodiments, other components not specifically shown in
The following paragraphs provide examples of various ones of the embodiments disclosed herein.
Example 1 provides an electronic assembly that includes a first die, including a first transmission line; a second die, including a second transmission line, where each of the first die and the second die includes a first face and an opposing second face, the first face of the second die is coupled to the second face of the first die (i.e., the second die is stacked above the first die), and each of the first transmission line and the second transmission line has a first end and an opposing second end; a first electrically conductive pathway between (i.e., electrically connecting, e.g., directly connecting) the first end of the first transmission line and a first connection point at the first face of the first die; a second electrically conductive pathway between (i.e., electrically connecting, e.g., directly connecting) the first end of the second transmission line and a second connection point at the first face of the first die; and a third electrically conductive pathway between (i.e., electrically connecting, e.g., directly connecting) the second end of the first transmission line and the second end of the second transmission line.
Example 2 provides the electronic assembly according to example 1, where the first die has a thickness below about 40 microns, e.g., between about 2 microns and 40 microns, between about 5 microns and 30 microns, or between about 10 microns and 30 microns. Other dies implementing other branches of the three-dimensional power combiner may have similar thicknesses.
Example 3 provides the electronic assembly according to examples 1 or 2, where the first conductive pathway includes a conductive via between (i.e., electrically connecting, e.g., directly connecting) the first end of the first transmission line and the first connection point at the first face of the first die.
Example 4 provides the electronic assembly according to any one of the preceding examples, where the second conductive pathway includes a direct bonding interconnect between (i.e., electrically connecting, e.g., directly connecting) the first die and the second die.
Example 5 provides the electronic assembly according to example 4, where the second conductive pathway further includes a conductive via in the first die, between (i.e., electrically connecting, e.g., directly connecting) the direct bonding interconnect at the second face of the first die and the second connection point at the first face of the first die.
Example 6 provides the electronic assembly according to examples 4 or 5, where the second conductive pathway further includes a conductive via in the second die, between (i.e., electrically connecting, e.g., directly connecting) the first end of the second transmission line and the direct bonding interconnect at the first face of the second die.
Example 7 provides the electronic assembly according to any one of the preceding examples, where a distance between the first die and the second die is below about 10 microns, e.g., below about 5 microns or below about 2 microns, e.g., between about 0.5 microns and 2 microns.
Example 8 provides the electronic assembly according to any one of the preceding examples, where no solder is present at an interface between the second face of the first die and the first face of the second die.
Example 9 provides the electronic assembly according to any one of the preceding examples, where the second transmission line is vertically aligned with the first transmission line (e.g., projections of the first and second transmission lines onto a plane parallel to the first or the second face of the first die may be overlapping).
Example 10 provides the electronic assembly according to any one of the preceding examples, further including a base die having a first face and an opposing second face, where the second face of the base die is coupled to the first face of the first die, the base die includes a first amplifier coupled (e.g., directly electrically connected) to the first connection point at the first face of the first die, and the base die further includes a second amplifier coupled (e.g., directly electrically connected) to the second connection point at the first face of the first die.
Example 11 provides the electronic assembly according to example 10, where: the base die further includes a third amplifier coupled (e.g., directly electrically connected) to the first connection point (e.g., 112-1) at the first face of the first die, and one of the first amplifier and the third amplifier is a power amplifier and another one of the first amplifier and the third amplifier is an LNA.
Example 12 provides the electronic assembly according to examples 10 or 11, further including an antenna module and a fourth electrically conductive pathway, where: the antenna module is coupled to the first face of the base die and includes an antenna unit, the fourth electrically conductive pathway is between the first face of the base die and the second face of the base die, one end of the fourth conductive pathway is coupled to the antenna unit, and another end of the fourth conductive pathway is coupled to the third conductive pathway.
Example 13 provides the electronic assembly according to examples 10 or 11, further including an antenna module and a fourth electrically conductive pathway, where: the antenna module is closer to the second face of the second die than the first face of the second die and includes an antenna unit, one end of the fourth conductive pathway is coupled to the antenna unit, and another end of the fourth conductive pathway is coupled to the third conductive pathway.
Example 14 provides an electronic assembly that includes a plurality of dies stacked above one another, and a three-dimensional power combiner, including a first branch in a first die of the plurality of dies, and further including a second branch in a second die of the plurality of dies.
Example 15 provides the electronic assembly according to example 14, further including a direct bonding interface between the first die and the second die.
Example 16 provides the electronic assembly according to example 15, where each of the first branch and the second branch includes a first end and a second end, the electronic assembly further includes a direct bonding interconnect that connects the first end of the first branch with the first end of the second branch, the second end of the first branch is connected to a first input or output terminal of the electronic assembly, and the second end of the second branch is connected to a second input or output terminal of the electronic assembly.
Example 17 provides the electronic assembly according to example 16, where the direct bonding interconnect is connected to a third input or output terminal of the electronic assembly, the first input or output terminal and the second input or output terminal are closer to a first face of the first die than to a second face of the first die, the second face of the first die being opposite the first face of the first die, and the third input or output terminal is closer to the second face of the first die.
Example 18 provides the electronic assembly according to any one of examples 14-17, where the first branch includes a first transmission line parallel to an interface between the first die and the second die, and the second branch includes a second transmission line parallel to the interface.
Example 19 provides a system that includes a circuit board; and an electronic assembly, communicatively coupled to the circuit board, where the electronic assembly includes a face of a first die direct bonded to a face of a second die, and a power combiner having a first branch in the first die and a second branch in the second die.
Example 20 provides the system of example 19, where the system further includes a display communicatively coupled to the circuit board.
The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.
