1. Field of the Invention
The present invention relates generally to semiconductor devices and fabrication, and more particularly a single-transistor memory device coupled to a three dimensional capacitor and methods for fabricating the same.
2. Description of Related Art
Semiconductor memory devices, in particular, random access memory devices, generally employ capacitors, which have the ability to retain a charge. This ability allows the capacitor to “remember” an energy level over a period of time, and thus can store data to be retrieved when needed.
One example of random access memory devices includes a dynamic random access memory (DRAM). In a DRAM cell, charge stored on a planar capacitor of the memory cell does not remain on the planar capacitor indefinitely due to a variety of leakage paths, which causes the memory cell to lose the data. To alleviate this problem, each memory cell in the DRAM must be periodically read, sensed, and re-written to a full level, generally requiring additional circuitry. Additionally, in order to increase the capacitive storage capability, the capacitors may be designed to a larger scale. The plates must be large enough to retain the energy level without being detrimentally affected by parasitic components or device noise.
However, as technology advances and smaller, faster devices are being implemented, the use of planar capacitor limits the scaling of DRAM cells. In particular, the packing density of DRAM cells is reduced and therefore, the number of available memory cells on a wafer is limited.
Another example of a random access memory device includes a static random access memory (SRAM) cell, which does not require the refresh operations like a DRAM memory cell. The SRAM cell can retain the stored information and consumes very little power during its standby state. However, the density of the storage elements in the SRAM is low compared to the density of the storage elements in the DRAM.
Any shortcoming mentioned above is not intended to be exhaustive, but rather is among many that tends to impair the effectiveness of previously known techniques for memory storage design however, shortcomings mentioned here are sufficient to demonstrate that the methodologies appearing in the art have not been satisfactory and that a significant need exists for the techniques described and claimed in this disclosure.
The present disclosure provides a three-dimensional, single transistor memory cell, which is considerably smaller in terms dimension compared to standard six transistor memory devices, and thus, allows for increased memory cell availability on a wafer.
In one respect, a three-dimensional capacitor may be coupled to a drain input of a multi-gate field effect transistor (MUGFET). The MUGFET may include a multi-fin MUGFET and the three-dimensional capacitor may be a multi-fin three-dimensional capacitor.
In other respects, a three-dimensional capacitor may be coupled to a drain input of a fin field effect transistor (finFET). The three-dimensional capacitor may be a multi-fin three-dimensional finFET type capacitor.
In some respects, a method for fabricating a single-transistor memory cell is provided. The method includes providing a substrate, such as an SOI substrate, bulk silicon substrate, strained silicon-on-insulator (sSOI) substrate, silicon-germanium-on-insulator (GOI) substrate, strained silicon-germanium-on-insulator (sGeOI) substrate, or silicon on sapphire (SoS) substrate. Next, the method provides steps for defining a source and drain and forming a channel between the source and drain and a gate area on the substrate.
The method also provides forming a first and second capacitor plate of a three-dimensional capacitor coupled to the drain of the transistor. In some embodiments, the first capacitor plate may be fabricated simultaneously with the step of forming the channel. Similarly, the second capacitor plate may be fabricated substantially simultaneously with the step of defining the gate area of the transistor.
The following drawings form part of the present specification and are included to further demonstrate certain aspects of the present invention. The figures are examples only. They do not limit the scope of the invention.
The disclosure and the various features and advantageous details are explained more fully with reference to the nonlimiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well known starting materials, processing techniques, components, and equipment are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only and not by way of limitation. Various substitutions, modifications, additions, and/or rearrangements within the spirit and/or scope of the underlying inventive concept will become apparent to those skilled in the art from this disclosure.
The disclosure provides a memory cell having one transistor coupled to a capacitor, as shown in the circuit diagram and corresponding layout of
In one embodiment, transistor 10 may be a multi-gate field effect transistor (MUGFET) on a SOI substrate. Alternatively, transistor 10 may be a Fin field effect transistor (finFET), a Π transistor, or an Ω transistor. The fabrication process of transistor 10 and capacitor 18 may be done using conventional techniques known in the art, and thus provides an inexpensive technique compared to other fabrication processes.
Referring again to
Referring to
In some embodiments, capacitor 28 may include a single fin capacitor coupled to a multiple fin MUGFET as shown in
Those with ordinary skill in the art may understand that fabrication steps including, without limitation, chemical vapor deposition (CVD), atomic layer deposition (ALD), wet etch, dry etch, etc., may be used. In one embodiment, to form channel 23 of a MUGFET and the capacitor bottom plate (e.g., the capacitor plate coupled to a terminal of a transistor) simultaneously, an implantation step may be done in the silicon on the buried oxide. One of ordinary skill in the art may recognize that the channel and the capacitor bottom plate may be fabricated separately, using for example, extra masking steps. Using an appropriate lithography process such as 248 nm, 193 nm, e-beam, spacer process, etc., a resist layer may be deposited and patterned such to define the fin, the source area, and drain area of the transistor. Additionally, the resist may be pattered to define the capacitor top plate and the contact area. The size of MUGFET may correspond to the minimum feature sizes varying for different implementations. Next, the silicon layer of substrate 100 may be etched using an etchant selective to the buried oxide. The resist layer may be ashed and the features are cleaned using for example, a wet cleaning solution (SPM/RCA) or Excalibur clean process.
In some embodiments, the transistor and capacitor 28 may be fabricated using films requiring a hard mask. The hard mask may be patterned using a photo resist layer and an anti-reflective coat layer. Next, the hard mask is then used to etch the silicon feature and stopped on the buried oxide.
In some embodiments, the first capacitor plate for capacitor 28 may be formed with a hydrogen (H2) anneal process, such that the interface roughness of the transistor and capacitor 28 is reduced. A H2 anneal may smooth the fin surfaces and round the exposed sharp corners. The hydrogen anneal process may be performed at about 800° C. and about 600 Torr or closer to atmospheric pressure may be more suitable for MuGFET structure and may be used for capacitor structures.
One of ordinary skill in the art will recognize that other sidewall smoothness methods may be used. For example, various oxidations of the etched surface and a selective wet strip may be used to smooth the sidewalls.
Next, a gate dielectric and polysilicon may be deposited and patterned to form gate 24 and the top plate of capacitor 28 (e.g., the capacitor plate coupled to ground as shown in
In
Next, the source and drain may be defined, as shown in
In
Similar fabrication steps such as those shown in
Additionally, the above fabrication steps may also be used to create a plurality of one transistor memory cells. The plurality of one transistor memory cells may be coupled, for example, in series to form a memory cell system.
All of the methods and devices disclosed and claimed can be made and executed without undue experimentation in light of the present disclosure. While the methods of this invention have been described in terms of embodiments, it will be apparent to those of skill in the art that variations may be applied to the methods and in the steps or in the sequence of steps of the method described herein without departing from the concept, spirit and scope of the invention. All such similar substitutes and modifications apparent to those skilled in the art are deemed to be within the spirit, scope, and concept of the disclosure as defined by the appended claims.