Patent Application
20240258437
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0011116, filed on Jan. 27, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
Inventive concepts relate to a Field Effect Transistor (FET), and more particularly, to a three dimensional (3D) stacked FET having a structure in which FETs are stacked.
Recently, down-scaling of semiconductor devices has been rapidly progressing. In addition, since a semiconductor device may require not only high operating speed but also operational accuracy, the structure of a transistor included in the semiconductor device is being optimized. In particular, as semiconductor devices are highly integrated, semiconductor devices may have three-dimensional transistors having a multi-gate structure. For example, a 3D transistor may be implemented in a form in which a gate surrounds an active fin formed on a substrate.
Inventive concepts provide a three dimensional (3D) stacked Field Effect Transistor (FET) capable of sufficiently securing a channel width without increasing a cell height.
In addition, inventive concepts are not limited to the above-mentioned aspects, and other aspects may be clearly understood by those skilled in the art from the description below.
According to an embodiment of inventive concepts, a three dimensional (3D) stacked Field Effect Transistor (FET) may include a back-side wiring layer including a first back-side power line and a second back-side power line each extending in a first direction; a first FET on the back-side wiring layer; a second FET over the first FET; a front-side wiring layer over the second FET, the front-side wiring layer extending in the first direction, and the front-side wiring layer including a front-side power line connected to the second back-side power line; a first through-electrode connecting the first FET to the second FET; and a second through-electrode connecting the front-side power line to the second aback-side power line. The first FET and the second FET may share a gate extending in a second direction. The second direction may be perpendicular to the first direction. Each of the first FET and the second FET may include a source and a drain respectively on both sides of the gate in the first direction, and a channel between the source and the drain and surrounded by the gate.
According to an embodiment of inventive concepts, a 3D stacked FET may include a back-side wiring layer including a first back-side power line and a second back-side power line each extending in a first direction; a first FET on the back-side wiring layer; a second FET over the first FET, a conductivity type of the second FET being different than a conductivity type of the first FET; a front-side wiring layer over the second FET, the front-side wiring layer extending in the first direction and including a front-side power line connected to the second back-side power line; a first through-electrode connecting the first FET to the second FET; and a second through-electrode connecting the front-side power line to the second back-side power line. The first FET and the second FET may share a first gate. The first FET and the second FET may be in a unit cell of the 3D stacked FET. The unit cell may correspond to an area between up to one-half of each of two other gates on opposite sides of the first gate in the first direction and between the first back-side power line and the second back-side power line in a second direction. In the unit cell, the first gate may be between the two other gates. The second direction may be perpendicular to the first direction. The unit cell may be among a plurality of unit cells repeatedly arranged in the first direction and the second direction.
According to an embodiment of inventive concepts, a 3D stacked FET may include a back-side wiring layer including a first back-side power line and a second back-side power line each extending in a first direction; a first FET on the back-side wiring layer; a second FET over the first FET, a conductivity type of the second FET being different than a conductivity type of the first FET; a front-side wiring layer over the second FET, the front-side wiring layer extending in the first direction, and the front-side wiring layer including a front-side power line connected to the second back-side power line; a first through-electrode connecting the first FET to the second FET; and a second through-electrode connecting the front-side power line to the second back-side power line. The first FET and the second FET may share a first gate. The first FET and the second FET may be in a unit cell of the 3D stacked FET. The unit cell may correspond to an area between up to one-half of each of two other gates on opposite sides of the first gate in the first direction and between the first back-side power line and the second back-side power line in a second direction. The second direction may be perpendicular to the first direction. In the unit cell, the first gate may be between the two other gates. Each of the first FET and the second FET may include a source and a drain respectively on both sides of the first gate in the first direction, and a channel between the source and the drain and surrounded by the first gate.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Embodiments of inventive concepts will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.
Referring to
The back-side wiring layer 110 may include a first back-side power line 112, a second back-side power line 114, and a back-side signal line 116. The first back-side power line 112 may extend in the x direction. The first back-side power line 112 may provide first power VDD, e.g., power of a positive potential, to the first FET 120 and the second FET 130.
The second back-side power line 114 may be spaced apart from the first back-side power line 112 in the y direction and extend in the x direction. The second back-side power line 114 may provide second power VSS, e.g., power at a negative potential or a ground potential, to the first FET 120 and the second FET 130.
The back-side signal line 116 may be disposed between the first back-side power line 112 and the second back-side power line 114 in the y-direction and extend in the x-direction. The back-side signal line 116 may be connected to a first source/drain (see S1/D1 of
In the 3D stacked FET 100 of this embodiment, the first back-side power line 112 and the second back-side power line 114 may be alternately disposed with the back-side signal line 116 disposed in the y direction. As may be seen from
The first FET 120 may be disposed on the back-side wiring layer 110 in the z direction. Also, the second FET 130 may be disposed above the first FET 120 in the z direction. That is, the second FET 130 may be stacked on top of the first FET 120. As such, the 3D stacked FET 100 of this embodiment may have a structure in which two FETs are stacked in the z direction. The stacked structure of the first FET 120 and the second FET 130 is described in more detail in the description of
In the 3D stacked FET 100 of this embodiment, the first FET 120 may be a PMOS FET and the second FET 130 may be an NMOS FET. However, in other embodiments, the first FET 120 may be an NMOS FET and the second FET 130 may be a PMOS FET. The first FET 120 and the second FET 130 may each include a gate Gc, a source/drain (see S1/D1 and S2/D2 in
Specifically, the first FET 120 may include a gate Gc, a first source/drain S1/D1, and a first channel MBC1 and the second FET 130 may include a gate Gc, second source/drain S2/D2, and a second channel MBC2. The first FET 120 and the second FET 130 may share the gate Gc.
The gate Gc may extend in the y direction. The gate Gc may surround the first channel MBC1 and the second channel MBC2 in a gate all around (GAA) structure. The active region ACT extends in the x direction and may include a lower first active region (refer to ACT1 in
Specifically, in the first FET 120, the first active regions ACT1 on both sides of the gate Gc in the x direction may constitute the first source/drain S1/D1, and the first active region ACT1 between the first source S1 and the first drain D1 may constitute the first channel MBC1. In addition, in the second FET 130, the second active region ACT2 on both sides of the gate Gc in the x direction may constitute the second source/drain S2/D2, and the second active region ACT2 between the second source S2 and the second drain D2 may constitute the second channel MBC2. Furthermore, each of the first channel MBC1 and the second channel MBC2 has a Multi-Bridge Channel (MBC) structure and may be surrounded on four sides by the gate Gc. Here, the four sides may include both sides in the y direction and both sides in the z direction. According to an embodiment, each of the first channel MBC1 and the second channel MBC2 may include at least two nano-sheets. However, in other embodiments, at least one of the first channel MBC1 and the second channel MBC2 may include only one nanosheet.
In the 3D stacked FET 100 of this embodiment, a unit cell UC corresponds to, for example, a standard cell and may thus be used as a basic layout when designing an integrated circuit. To briefly explain the standard cell, as semiconductor devices have recently become highly integrated, a lot of time and money is required to design an integrated circuit, especially a layout for an element area. Therefore, as a kind of technology for saving this, a standard cell-based layout design technique may be used. The standard cell-based layout design technique may reduce the time required for layout design by arranging and wiring where necessary during layout design after designing logic elements such as OR gates or AND gates that are used repeatedly as standard cells in advance and storing the logic elements in a computer system.
For example, standard cells may include basic cells, such as an AND, an OR, a NOR, an inverter, a NAND, a NOR, and the like, complex cells, such as an OR/AND/INVERTER (OAI) and an AND/OR/INVERTER (AOI), and storage elements, such as simple master-slave flip-flops and latches.
The standard cell method is a method of designing a dedicated large-scale integrated (LSI) circuit tailored to the needs of customers or users by preparing logic circuit blocks having various functions, that is, cells in advance and combining these cells arbitrarily. Cells may be designed and verified in advance and registered in advance in a computer, and logic design, placement, wiring, and the like may be performed by combining the registered cells using computer aided design (CAD).
Specifically, in the case of designing/manufacturing an LSI circuit, if standardized logic circuit blocks of a certain scale, that is, standard cells, are already stored in a library, a standard cell suitable for the current design purpose is taken out of the library and placed as a plurality of cells on the chip, and by performing optimum wiring with the shortest wiring length in the wiring space between cells, it is possible to design the entire circuit. As the types of cells stored in the library become richer, design becomes more flexible, and as such, the possibility of optimal design of the chip may increase.
A unit cell of the 3D stacked FET 100 of this embodiment may include, for example, an inverter. However, in the 3D stacked FET 100 of this embodiment, a unit cell is not limited to an inverter and may include other logic elements. The inverter may be implemented by connecting a MOSFET and another MOSFET in series. Specifically, in the 3D stacked FET 100 of this embodiment, the first FET 120 corresponds to a PMOS FET, the first drain D1 may be disposed on the left side of the gate Gc, and the first source S1 may be disposed on the right side of the gate Gc in the x direction. In addition, the second FET 130 corresponds to an NMOS FET, the second source S2 may be disposed on the left side of the gate Gc, and the second drain D2 may be disposed on the right side of the gate Gc in the x direction. In addition, the first drain D1 of the first FET 120 may be connected to the first back-side power line 112 through a lower contact portion 170, and the second source S2 of the second FET 130 may be connected to a front-side power line 142 through an upper contact portion 180. The connection relationship between the first FET 120 and the second FET 130 and the back-side wiring layer 110 and the front-side wiring layer 140 is described in more detail in the description of
The front-side wiring layer 140 may include the front-side power line 142 and a front-side signal line 144. The front-side power line 142 may extend in the x direction. The front-side power line 142 may provide second power VSS, for example, power at a negative potential or a ground potential, to the second FET 130. The front-side power line 142 may be connected to the second back-side power line 114 through the second through electrode 160 disposed in a power tap cell PTC.
A plurality of front-side signal lines 144 are spaced apart from each other in the y-direction and may extend in the x-direction. The front-side signal line 144 may be connected to the second source/drain S2/D2 of the second FET 130 through a signal via (see 195 in
The front-side wiring layer 140 may correspond to the lowermost wiring layer, e.g., the wiring layer M1, among wiring layers having a multilayer structure disposed on the front side of the substrate. As shown in
The first through electrode 150 may connect the first FET 120 and the second FET 130 to each other in the z direction. Specifically, the first through electrode 150 may extend in the z direction and connect the first source S1 of the first FET 120 to the second drain D2 of the second FET 130.
As described above, the second through electrode 160 may be disposed in the power tap cell PTC and connect the front-side power line 142 and the second back-side power line 114 to each other. One power tap cell PTC may be disposed for every tens to hundreds of contact poly pitches (CPPs) in the x direction. For example, in the 3D stacked FET 100 of this embodiment, one power tap cell PTC may be disposed for every 60 or so CPPs.
For reference, in the 3D stacked FET 100 of this embodiment, the CPP may refer to a gate pitch in the x direction. In addition, in the 3D stacked FET 100 of this embodiment, two CPPs may constitute one unit cell UC. More specifically, in the 3D stacked FET 100 of this embodiment, the unit cell UC may be defined as an area up to ½ of each of two outer gates Go1 and Go2 on both sides of the gate Gc at the center in the x direction, and an area including the first back-side power line 112 and the second back-side power line 114 in the y-direction. These unit cells UC may be arranged in a two-dimensional array structure in the x and y directions.
Referring to
Meanwhile, on the positions of the cutting lines I-I′ and II-II′ in the x direction, the first and second channels MBC1 and MBC2 may not be visible in
Additionally, in
Specifically, a connection relationship between the first FET 120 and the second FET 130 and the back-side wiring layer 110 and the front-side wiring layer 140 will be described.
As shown in
As shown in
Also, the second source S2 of the second FET 130 may be connected to the front-side power line 142 through the upper contact portion 180. The upper contact portion 180 may include a second source contact 182 and a second power via 184. The second source contact 182 may contact the second source S2 and extend in the y direction. The second power via 184 may connect the second source contact 182 to the front-side power line 142. Accordingly, at least a portion of the second source contact 182 and the front-side power line 142 overlap in the z direction, and a second power via 184 may be disposed on the overlapped portion to connect the second source contact 182 to the front-side power line 142.
As may be seen from
As shown in
In addition, the second drain contact 194 may be connected to the front-side signal line 144 of the front-side wiring layer 140 through the signal via 195. For example, an output signal of the inverter may be output through the signal via 195. In addition, a gate via 197 may be disposed on the gate Gc and the gate via 197 may be connected to the front-side signal line 144 of the front-side wiring layer 140. For example, an input signal may be applied to the inverter through the gate via 197. For reference, here, the front-side signal line 144 connected to the signal via 195 and the front-side signal line 144 connected to the gate via 197 may be different signal lines.
As may be seen from
For reference, the active region ACT may include a semiconductor material, such as Si, SiGe, Ge, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP. In the 3D stacked FET 100 of this embodiment, the active region ACT may include Si or SiGe.
In addition, each of the gate Gc and the outer gates Go1 and Go2 may include a gate dielectric layer, one or more work function control layers, and a gate electrode layer. The gate dielectric layer may include, for example, silicon oxide, silicon nitride, high-k dielectric materials, other dielectric materials, and/or combinations thereof, and may include at least one of dielectric materials. High-k dielectric materials may include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloys, other high-k dielectric materials, and/or a combination thereof. In some embodiments, the gate dielectric layer may include an interfacial layer formed between the channel layers and the dielectric material. In some embodiments, the gate dielectric layer may be formed using an atomic layer deposition (ALD) process to have a uniform thickness around each of the channel layers. However, the method of forming the gate dielectric layer is not limited to the ALD process. In some embodiments, the gate dielectric layer may have a thickness ranging from about 1 nm to about 6 nm.
A gate electrode layer may be formed on the gate dielectric layer to surround each of the first and second channels MBC1 and MBC2. The gate electrode layer may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other conductive materials, and/or combinations thereof, and may include one or more conductive materials.
One or more work function control layers may be disposed on the gate dielectric layer. The work function control layer may include a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of a combination of two or more of these materials.
Furthermore, the contacts 172, 182, 192, and 194 and/or the vias 174, 184, 195, and 197 connected to the first FET 120 and the second FET 130 may include the same conductive material or different conductive materials. For example, the conductive material may include Co, Ni, W, Ti, Ta, Cu, Al, TiN, TaN, or other conductive materials. In some embodiments, a silicide layer may be formed on the first and second sources/drains S1/D1 and S2/D2 prior to forming the conductive material. The silicide layer may include at least one of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi.
In some embodiments, the back-side wiring layer 110 and the front-side wiring layer 140 may include at least one of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN.
In some embodiments, the first channel MBC1 of the first FET 120 and the second channel MBC2 of the second FET 130 may include the same material, e.g., Si. In other embodiments, the first channel MBC1 and the second channel MBC2 may include different materials. For example, the first channel MBC1 may include SiGe and the second channel MBC2 may include Si.
In the 3D stacked FET 100 of this embodiment, the second source S2 of the second FET 130 may be connected to the second back-side power line 114 through the second source contact 182, the second power via 184, the front-side power line 142, and the second through electrode 160. Based on this power wire connection structure, in the 3D stacked FET 100 of this embodiment, one through electrode in the unit cell UC may be omitted. Accordingly, the 3D stacked FET 100 of the present embodiment may sufficiently secure a channel width without increasing the cell height CH in the y direction. The omission of one through electrode and the securing of the channel width is described in more detail in the description of
Referring to
For reference, the SDB may have substantially the same width as the gates, that is, the gate Gc and the outer gates Go1 and Go2, in the x direction. For example, in the SDB, an insulating layer having substantially the same width as the gate may extend into the semiconductor substrate to isolate the active region ACT. Unlike a double diffusion break (DDB), a separate dummy gate does not exist in the SDB, and an upper portion of an insulating layer constituting the SDB may protrude on the substrate in correspondence with the gate.
Furthermore, the DDB, as an active separation structure different from the SDB, may be formed across two gates. For example, the DDB may be formed by disposing an insulating layer in a buried structure under two adjacent gates in the x direction. Accordingly, the DDB has a width corresponding to a pitch between gates in the x direction, e.g., CPP, and in the DDB, the upper two gates may correspond to dummy gates.
On the other hand, when considering the area of a cell, two cells including DDB may be larger than two cells including SDB by 1 CPP in the x direction. Therefore, cells including the SDB may be useful in terms of area. In addition, the insulating layers constituting the DDB and the SDB may include a compressive stress material and/or a tensile stress material. Here, the compressive stress material is a material capable of applying compressive stress to the active region, and the tensile stress material is a material capable of applying tensile stress to the active region. For example, the insulating layer of the SDB may include silicon nitride, and the insulating layer of the DDB may include tetraethoxysilane (TEOS). However, the materials of the insulating layers of the DDB and SDB are not limited to the above materials.
As shown in
For reference, in the case of a DRAM chip, the through electrode has a relatively large length in μm, but in the 3D stacked FET 100 of this embodiment, the first through electrode 150 or the second through electrode 160 may have a very small length of several tens to hundreds of nm. Accordingly, the first through electrode 150 or the second through electrode 160 may be referred to as a tall via, nano TVS, or tap via. Here, the nano TSV may refer to an electrode having a nano size and penetrating Si.
On the other hand, as shown in
In addition, although not shown in the cross-sectional view of
Referring to
The first FET 120 may be disposed on the back-side wiring layer 110. In
A second FET 130 may be disposed on the first FET 120. In
In the z direction, the front-side wiring layer 140 may be disposed at the top. In
In the 3D stacked FET 100 of this embodiment, the second source S2 of the second FET 130 may be connected to the second back-side power line 114 through the second source contact 182, the second power via 184, the front-side power line 142, and the second through electrode 160. Based on this power wire connection structure, in the 3D stacked FET 100 of this embodiment, one through electrode in the unit cell UC may be omitted. Accordingly, the width of the channel may be sufficiently secured without increasing the cell height CH in the y-direction.
Referring to
In addition, in the 3D stacked FET 100 of this embodiment, the first drain D1 of the first FET 120 may be connected to the first back-side power line 112 through the first drain contact 172 and the first power via 174, and the second source S2 of the second FET 130 may be connected to the front-side power line 142 through the second source contact 182 and the second power via 184. Accordingly, a through electrode connecting the second source S2 of the second FET 130 to the second back-side power line 114 may not be disposed in the unit cell.
Accordingly, the 3D stacked FET 100 according to the present embodiment may sufficiently secure the channel width in the y-direction without increasing the cell height CH1 in the y-direction. In
Referring to
On the other hand, in the 3D stacked FET Com. of the comparative example, the first drain D1 of the first FET FET1 may be connected to the first back-side power line VDD through the bottom drain contact CAb2 and the first power via VA1, and the second source S2 of the second FET FET2 may be connected to the second back-side power line VSS through the top source contact CAt2 and the second through electrode TV2. Accordingly, two through electrodes (the first and second through electrodes TV1 and TV2) may be disposed in the y direction in the unit cell.
Accordingly, the cell height CH2 of the 3D stacked FET Com. of the comparative example may increase in the y direction. For reference, when the through electrode is disposed, a minimum distance from an adjacent active, e.g., source/drain may be required. Specifically, in
On the other hand, in the case of the 3D stacked FET 100 of this embodiment, only the first through electrode 150 is disposed in the unit cell UC, and therefore, since only a distance {circle around (1)} between the first source S1 and the first through electrode 150 is required in the y direction, a sufficient channel width may be secured without increasing the cell height CH1.
A unit cell UC of the 3D stacked FET 100 of this embodiment may include an inverter. By connecting the second source S2 of the NMOS FET of the inverter, that is, the second source S2 of the second FET 130 to the second back-side power line 114 of the back-side wiring layer 110 through the wiring layer M1, for example, the front-side power line 142 of the front-side wiring layer 140 and the second through electrode 160 of the power tap cell PTC, one through electrode in the unit cell UC of the inverter may be omitted. The concept of detouring power transmission using the wiring layer M1 and the through electrode of the power tap cell PTC is not limited to the inverter. For example, the detouring concept of power transfer may be applied to various logic circuits such as an AND and an OR employing a standard cell structure. In addition, the concept of bypassing power transfer may be applied not only to 3D stacked FETs but also to 2D FETs. In the case of a 2D FET, since the length of the through electrode is not large, the necessity of removing the through electrode may not be great. However, there is still an advantage of omitting the through electrode in terms of maintaining or reducing the cell height.
Referring to
In the 3D stacked FET 100a of this embodiment, only the first through electrode 150 is disposed in the unit cell in the y direction, and the second source S2 of the second FET 130 may be connected to the second back-side power line 114 through the second source contact 182, the second power via 184, the front-side power line 142, and the second through electrode 160.
Referring to
Referring to
Referring to
Referring to
One or more of the elements disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.
While embodiments of inventive concepts have been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0011116 | Jan 2023 | KR | national |
