Timing generator circuit

Abstract

A timing generator circuit according to the present invention receives rate signal pulses and delay assignment data composed of rate number data and clock number data, and outputs timing signals delayed from the input timing of the rate signal pulses by intervals corresponding to the delay assignment data. The timing generator circuit comprises a counter for counting clock signals, which is reset by means of the rate signal pulses; a shift register for sequentially shifting the delay assignment data or data corresponding to the delay assignment data by means of the rate signal pulses; a coincidence detector for detecting data corresponding to predetermined rate number data from among output data from a stage of the shift register, and outputting pulses when clock number data contained in the output data coincide with count values of the counter; and a multiplexer for multiplexing the pulses outputted from the coincidence detector section and outputting the result as a timing signal.

Description

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The present invention relates to timing generator circuits used in TG (timing generator) sections of IC testers and the like, and more specifically to timing generator circuits which output rate signal pulses of undefined periods after delaying them by the intervals of clock periods assigned by delay assignment data which are provided in synchronization.

2. Background Art

In IC tests due to IC testers, constant measurement sequences are carried out at defined timings. For example, IC function tests are basically performed by the repetition of the following procedure.

a. Test patterns for the function test are read one at a time from a memory at timings which are defined by a program (a measurement program which determines the measurement procedure for the relevant IC). b. Patterns corresponding to the IC input terminals are selected from among the binary data of "1"'s and "0"'s forming the readout pattern, and a voltage waveform corresponding to these "1"'s and "0"'s is supplied to each input terminal of the IC at a timing determined by the program. c. As a result, response waveforms obtained from each output terminal of the IC are sampled at timings determined by the program, and the results are collated with the test patterns in order to judge whether or not the IC is functioning normally.

In order to properly perform these types of function tests, timing control must be performed so that the procedure can be performed with the determined timings.

Additionally, depending on the IC which is undergoing the test, instead of supplying the binary data forming a pattern immediately as an input waveform to the IC, there may be cases wherein a voltage waveform corresponding to the binary data is supplied to the IC after a time lag of a desired interval, or wherein a multiplexed clock signal is generated in accordance with the binary data and supplied to the IC. These types of tests require more complex timing control schemes.

As means for performing this type of timing control, various types of timing generator circuits are provided in IC testers. FIG. 5 shows an example of the structure of such a timing generator circuit. This timing generator circuit operates in synchronization with a clock signal .phi..sub.0 having a constant frequency f.sub.0, and delays rate signal pulses supplied from other circuitry inside the tester by a time interval assigned at a resolution of 1/f.sub.0, then outputs them as timing signals. Additionally, in this example, the structure is such as to be capable of delaying the rate signal pulses by 4 rates (wherein 1 rate is the interval between the rate signal pulses).

As shown in FIG. 5, this timing generator circuit comprises a demultiplexer 11, a counter section 12 and a multiplexer 13.

The demultiplexer 11 is a circuit which quadruple-interleaves delay assignment data D.sub.0 and a rate pulse signal T.sub.0 supplied from a control section (IC tester control system) which is not shown in the drawing, then outputs the results from first through fourth output terminals. That is, if this demultiplexer 11 outputs delay assignment data D.sub.0 and a rate signal pulse T.sub.0 supplied at a certain time from the first output terminal, the next delay assignment data D.sub.0 and rate signal pulse T.sub.0 are outputted from the second output terminal, and the next delay assignment data D.sub.0 and rate signal pulse T.sub.0 are outputted from the third output terminal, so as to output the delay assignment data D.sub.0 and rate signal pulse T.sub.0 while sequentially switching the output terminal.

The counter section 12 has four internal down-counters 12.sub.A .about.12.sub.D. These down-counters 12.sub.A .about.12.sub.D have mutually independent load input terminals LD and data input terminals DATA. The rate signal pulse T.sub.0 and delay assignment data D.sub.0 quadruple-interleaved by the demultiplexer 11 are respectively supplied to the load input terminal LD and the data input terminal DATA of each down-counter. Additionally, the down-counters 12.sub.A .about.12.sub.D each count down in accordance with a clock signal .phi..sub.0 of frequency f.sub.0, and output a pulse when the count value reaches "0". The multiplexer 13 multiplexes the four pulses obtained from these down-counters 12.sub.A .about.12.sub.D, then outputs the result as timing signal T.sub.OUT.

As explained above, the demultiplexer 11 quadruple-interleaves and outputs rate signal pulses T.sub.0 and delay assignment data D.sub.0. Therefore, when considering the down-counters 12.sub.A .about.12.sub.D, each down-counter is supplied with a rate signal pulse T.sub.0 and delay assignment data D.sub.0 for each four rate signal pulses that arrive from the demultiplexer 11, and the delay assignment data D.sub.0 is assigned as the initial count value. Each down-counter counts down from this initial value with the clock signal .phi..sub.0 and generates a pulse when the count value becomes "0". That is, the down-counters 12.sub.A .about.12.sub.D are able to count over three intervals of the rate signal pulses, i.e. over four rates; therefore, the rate signal pulses can be delayed by four rates.

FIG. 6 is a time chart showing the operations of the timing generator circuit. Hereinbelow, the operations of the timing generator circuit will be explained with reference to the diagram. In this diagram, N.sub.1 .about.N.sub.4 are the count values of the respective down-counters 12.sub.A .about.12.sub.D, T.sub.1 .about.T.sub.4 are the pulses outputted from the respective down-counters 12.sub.A .about.12.sub.D, and T.sub.OUT is a timing signal outputted from the multiplexer 13.

First, a rate signal pulse T.sub.0 (t.sub.1) and delay assignment data D.sub.0 (d.sub.1) are supplied, then inputted to the down-counter 12.sub.B via the demultiplexer 11. In this example, a "7" which orders a "delay of 7 clock minutes" is supplied as the delay assignment data D.sub.0 (d.sub.1). Therefore, a "7" is assigned to the down-counter 12.sub.B, and a countdown is started with this "7" as the initial value in accordance with the clock signal .phi..sub.0. In a similar manner, when the next rate signal pulse T.sub.0 (t.sub.2) and delay assignment data D.sub.0 (d.sub.2) (="5") are supplied, a "5" is assigned to the down-counter 12.sub.C via the demultiplexer 11. At this time, the count value N.sub.2 of the down-counter 12.sub.B is "4", and a parallel countdown is performed in accordance with the clock signal .phi..sub.0 by the down-counters 12.sub.B and 12.sub.C.

When the next rate signal pulse T.sub.0 (t.sub.3) and delay assignment data D.sub.0 (d.sub.3) (="5") are supplied, a "5" is assigned to the down-counter 12.sub.D via the demultiplexer 11. At this time, the count value N.sub.2 of the down-counter 12.sub.B is "3", the count value N.sub.3 of the down-counter 12.sub.C is "4", and a parallel countdown is performed in accordance with the clock signal .phi..sub.0 by the down-counters 12.sub.B and 12.sub.C and 12.sub.D.

When the next rate signal pulse T.sub.0 (t.sub.4) and delay assignment data D.sub.0 (d.sub.4) (="4") are supplied, a "4" is assigned to the down-counter 12.sub.A via the demultiplexer 11. At this time, the count values of the down-counters 12.sub.B, 12.sub.C and 12.sub.D are "1", "2" and "3", and a parallel countdown is performed by all of the down-counters. When the next clock signal .phi..sub.0 is supplied, the value at the down-counter 12.sub.B becomes "0", so that the down-counter 12.sub.B generates a pulse T.sub.2 and stops the countdown. Thereafter, the count values of the down-counters 12.sub.C, 12.sub.D and 12.sub.A sequentially become "0", so that each down-counter sequentially outputs a pulse T.sub.3, T.sub.4 and T.sub.1, then stops the count. These pulses are multiplexed by the multiplexer 13 and supplied to the circuits inside the IC tester as timing signal T.sub.OUT so as to be used for timing control in the procedure for creating voltage waveforms to be supplied to the IC being tested.

In order to form IC testers which are capable of high-precision measurements, the resolution of the generation timing of the timing signals must be increased. Furthermore, in order to increase the resolution, the frequency f.sub.0 of the clock signal .phi..sub.0 supplied to the counter section 12 must be increased. However, the conventional timing generator circuit described above has a structure wherein n (n=4 in FIG. 5) down-counters are connected in parallel inside the counter section 12, so as to require a large amount of hardware which operates at high speeds of frequency f.sub.0, thereby resulting in considerable power consumption and a high cost.

SUMMARY OF THE INVENTION

The present invention has been achieved in consideration of the above situations, and has the object of offering a timing generator circuit which is capable of generating high-resolution timing signals without increasing the amount of circuitry or consuming large amounts of power.

In order to resolve the above-mentioned problems, the present invention offers timing generator circuit for receiving rate signal pulses and delay assignment data composed of rate number data and clock number data, and outputting timing signals delayed from the input timing of the rate signal pulses by intervals corresponding to the delay assignment data; comprising a counter for counting clock signals, which is reset by means of the rate signal pulses; a shift register for sequentially shifting the delay assignment data or data corresponding to the delay assignment data by means of the rate signal pulses; a coincidence detector section for detecting data corresponding to predetermined rate number data from among output data from a stage of the shift register, and outputting pulses when clock number data contained in the output data coincide with count values of the counter; and a multiplexer section for multiplexing the pulses outputted from the coincidence detector section and outputting the result as a timing signal.

In the timing generator circuit according to the present invention, there is only a single counter which operates by means of a high-speed clock signal, and the shift register contains very little hardware while operating on a rate signal pulse with a frequency lower than the clock signal. Therefore, the energy consumption can be reduced. Additionally, the amount of hardware in the circuit overall can also be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a timing generator circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operations of a timing generator circuit according to a first embodiment of the present invention.

FIG. 3 is a block diagram showing a timing generator circuit according to a second embodiment of the present invention.

FIG. 4 is a time chart showing the operations of a timing generator circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of the structure of a conventional timing generator circuit.

FIG. 6 is a time chart showing the operations of a conventional timing generator circuit.

PREFERRED EMBODIMENTS OF THE INVENTION

Hereinbelow, embodiments of the present invention will be explained with reference to the drawings.

�First Embodiment!

FIG. 1 is a block diagram showing a timing generator circuit according to a first embodiment of the present invention, which is capable of delaying for up to 4 rates. In the drawing, reference numeral 1 denotes an up-counter, reference numeral 2 denotes a decoder, reference numeral 3 denotes a four-stage shift register, reference numeral 4 denotes a coincidence detector, and reference numeral 5 denotes a multiplexer. This timing generator circuit is inputted with a rate signal pulse T.sub.0 having an undefined period, and delay assignment data D.sub.0 which is synchronized therewith. The delay assignment data D.sub.0 is composed of rate number data D.sub.1 for assigning the number of rates to be delayed, and clock number data D.sub.2 for assigning the delay time within the rates.

The up-counter 1 receives the rate signal pulse T.sub.0 inputted to the timing generator circuit as a reset input and the clock signal .phi..sub.0 of frequency f.sub.0 as a clock input, then counts up in accordance with the clock signal .phi..sub.0.

The decoder 2 is a circuit for decoding the rate number data D.sub.1 inputted to the timing generator circuit and outputting the result as signals EN.sub.A .about.EN.sub.D. In the present embodiment, the signals EN.sub.A .about.EN.sub.D each go to level H when the rate number data D.sub.1 are "0".about."3".

The shift register 3 receives data composed of the output signals EN.sub.A .about.EN.sub.D of the decoder 2 and the clock number data D.sub.2 as input data, and comprises four-staged latches 3.sub.A .about.3.sub.D having the rate signal pulse T.sub.0 as the clock. Of the data outputted from the latch 3.sub.A of the first stage, the portion corresponding to the signal EN.sub.A is outputted as the output signal E.sub.A of the shift register 3, and the portion corresponding to the clock number data D.sub.2 is outputted as data D.sub.A. Additionally, of the data outputted from the latch 3.sub.B of the second stage, the portion corresponding to the signal EN.sub.B is outputted as the output signal E.sub.B of the shift register 3, and the portion corresponding to the clock number data D.sub.2 is outputted as data D.sub.B. Similarly, the signals E.sub.C and data D.sub.C are outputted from the latch 3.sub.C of the third stage, and the signals E.sub.D and data D.sub.D are outputted from the latch 3.sub.D of the fourth stage.

The coincidence detector 4 has a quadruple-parallel structure, and comprises coincidence detector circuits 41.sub.A .about.41.sub.D having enable functions, and pulse generator circuits 42.sub.A .about.42.sub.D which are respectively connected in series therewith. The output signal E.sub.A of the shift register 3 is inputted to the enable input terminal EN of the coincidence detector 41.sub.A, the output signal D.sub.A of the shift register 3 is inputted to the first data input terminal A, and the count value N of the up-counter 1 is inputted to the second data input terminal B. Here, when the input signal level at the enable input terminal EN is at level H and the output signal D.sub.A of the shift register 3 corresponds with the count value N of the up-counter 1, the output signal of the coincidence detector circuit 41.sub.A is created, in response to which a single pulse T.sub.A is generated from the pulse generator circuit 42.sub.A. The same occurs with the coincidence detector circuits 41.sub.B .about.41.sub.D and the pulse generator circuits 42.sub.B .about.42.sub.D. The multiplexer 5 multiplexes the pulses T.sub.A.about.T.sub.D which are outputted in parallel from the pulse generator circuits 42.sub.A .about.42.sub.D of the coincidence detector 4 into a single signal which is outputted as a timing signal T.sub.OUT.

FIG. 2 is a time chart showing the operations of a timing generator circuit according to a first embodiment of the present invention. Hereinbelow, the operations of the present embodiment will be explained with reference to this diagram.

First, a first rate signal pulse T.sub.0 (t.sub.1) and delay assignment data D.sub.0 for assigning the delay amount of "3 rates+1 clock period" is supplied to this timing generator circuit. In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (="3") assigning a delay of 3 rates and clock number data D.sub.2 (="1") assigning a delay of 1 clock period. The rate number data D.sub.1 (="3") is inputted to the decoder 2. As a result, only the signal EN.sub.D of the output signals EN.sub.A .about.EN.sub.D of the decoder 2 goes to level H, and the others become level L. Then, input data composed of these signals EN.sub.A .about.EN.sub.D and the clock number data D.sub.2 (="1") are written into the first latch 3.sub.A of the shift register 3 by means of the rate signal pulse T.sub.0 (t.sub.1).

The clock signal data D.sub.2 (d.sub.1) (="1") written into the first latch 3.sub.A is supplied to the coincidence detector circuit 41.sub.A as data D.sub.A. However, at that time, an L-level signal E.sub.A (=EN.sub.A) is supplied from the first latch 3.sub.A to the enable terminal EN of the first coincidence detector circuit 41.sub.A. Consequently, the operation of the coincidence detector circuit 41.sub.A is prohibited.

Next, a second rate signal pulse T.sub.0 (t.sub.2) is supplied along with delay assignment data D.sub.0 (d.sub.2) for assigning a delay of "2 rates+2 clock periods". In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (d.sub.2) (="2") assigning a delay of 2 rates and clock number data D.sub.2 (d.sub.2) (="2") assigning a delay of 2 clock periods. As a result of the rate number data D.sub.1 (d.sub.2) (="2") being supplied to the decoder 2, the signal EN.sub.C goes to level H. Then, due to the second rate signal pulse T.sub.0 (t.sub.2), the signal EN.sub.B (=L), signal EN.sub.C (=L), signal EN.sub.D (=H) and the clock number data D.sub.2 (d.sub.1) (="1") stored in the first latch 3.sub.A are shifted to the second latch 3.sub.B.

Then, the clock signal data D.sub.2 (d.sub.2) written into the first latch 3.sub.A is inputted to the coincidence detector circuit 41.sub.A as data D.sub.A, while an L-level signal E.sub.A (=EN.sub.A) is supplied to the enable terminal EN of the first coincidence detector circuit 41.sub.A. Consequently, the operation of the coincidence detector circuit 41.sub.A is prohibited. Additionally, the clock number data D.sub.2 (d.sub.1) shifted to the second latch 3.sub.B is inputted to the second coincidence detector circuit 41.sub.B as data D.sub.B, while an L-level signal E.sub.B (=EN.sub.B) is supplied to the enable terminal EN of the second coincidence detector circuit 41.sub.B. Consequently, the operation of the coincidence detector circuit 41.sub.B is also prohibited.

Next, a third rate signal pulse T.sub.0 (t.sub.3) is supplied along with delay assignment data D.sub.0 (d.sub.3) for assigning a delay of "1 rate+3 clock periods". In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (d.sub.3) (="1") assigning a delay of 1 rate and clock number data D.sub.2 (d.sub.3) (="3") assigning a delay of 3 clock periods. As a result of the rate number data D.sub.1 (d.sub.3) (="1") being supplied to the decoder 2, the signal EN.sub.B goes to level H. Then, due to the third rate signal pulse T.sub.0 (t.sub.3), signal EN.sub.C (=H), signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.2) (="2") stored in the second latch 3.sub.B are shifted to the third latch 3.sub.C. Additionally, the signal EN.sub.B (=L), signal EN.sub.C (=H), signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.2) (="2") stored in the first latch 3.sub.A are shifted to the second latch 3.sub.B. Furthermore, input data composed of the output signals EN.sub.A .about.EN.sub.D (only EN.sub.B is at level H) of the decoder 2 and the clock signal data D.sub.2 (d.sub.3) (="3") are written into the first latch 3.sub.A.

Then, the clock signal data D.sub.2 (d.sub.3) written into the first latch 3.sub.A is inputted to the coincidence detector circuit 41.sub.A as data D.sub.A, while an L-level signal EA (=EN.sub.A) is supplied to the enable terminal EN of the first coincidence detector circuit 41.sub.A. Consequently, the operation of the coincidence detector circuit 41.sub.A is prohibited. Additionally, the clock number data D.sub.2 (d.sub.2) shifted to the second latch 3.sub.B is inputted to the second coincidence detector circuit 41.sub.B as data D.sub.B, while an L-level signal E.sub.B (=EN.sub.B) is supplied to the enable terminal EN of the second coincidence detector circuit 41.sub.B. Consequently, the operation of the coincidence detector circuit 41.sub.B is also prohibited. Furthermore, the clock number data D.sub.2 (d.sub.1) shifted to the third latch 3.sub.C is inputted to the third coincidence detector circuit 41.sub.C as data D.sub.C, while an L-level signal E.sub.C (=EN.sub.C) is supplied to the enable terminal EN of the third coincidence detector circuit 41.sub.C. Consequently, the operation of the coincidence detector circuit 41.sub.C is also prohibited.

Next, a fourth rate signal pulse T.sub.0 (t.sub.4) is supplied along with delay assignment data D.sub.0 (d.sub.4) for assigning a delay of "0 rates+4 clock periods". In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (d.sub.4) (="0") assigning a delay of 0 rates and clock number data D.sub.2 (d.sub.4) (="4") assigning a delay of 4 clock periods. As a result of the rate number data D.sub.1 (d.sub.4) (="0") being supplied to the decoder 2, the signal EN.sub.A goes to level H. Then, due to the fourth rate signal pulse T.sub.0 (t.sub.4), the signal EN.sub.D (=H) and the clock signal data D.sub.2 (d.sub.1) (="1") are shifted to the fourth latch 3.sub.D. Additionally, the signal EN.sub.C (=H), signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.2) (="2") stored in the second latch 3.sub.B are shifted to the third latch 3.sub.C. Additionally, the signal EN.sub.B (=H), signal EN.sub.C (=L), signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.3) (="3") stored in the first latch 3.sub.A are shifted to the second latch 3.sub.B. Furthermore, input data composed of the output signals EN.sub.A .about.EN.sub.D (only EN.sub.A is at level H) of the decoder 2 and the clock signal data D.sub.2 (d.sub.4) (="4") are written into the first latch 3.sub.A.

The clock signal data D.sub.2 (d.sub.4) (="4") written in the first latch 3.sub.A are inputted to the first coincidence circuit 41.sub.A as data D.sub.A. Then, since an H level signal E.sub.A (=EN.sub.A) is supplied to the enable terminal EN of the first coincidence detector circuit 41.sub.A, operation of the coincidence circuit 41.sub.A is allowed, and a comparison is made between the count value N of the up-counter 1 and the clock number data D.sub.2 (d.sub.4) (="4"). Therefore, the generation of 4 clock signals .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in the count value N of the up-counter 1 becoming "4", and a coincidence detection signal indicating that the two values coincide is outputted by the coincidence detector circuit 41.sub.A. As a result, a pulse T.sub.A is outputted from the pulse generator circuit 42.sub.A.

On the other hand, the clock signal data D.sub.2 (d.sub.3) (="3") written in the second latch 3.sub.B are inputted to the second coincidence circuit 41.sub.B as data D.sub.B. Then, since an H level signal E.sub.B (=EN.sub.B) is supplied to the enable terminal EN of the second coincidence detector circuit 41.sub.B, operation of the coincidence circuit 41.sub.B is allowed, and a comparison is made between the count value N of the up-counter 1 and the clock number data D.sub.2 (d.sub.3) (="3"). Therefore, the generation of 3 clock signals .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in the count value N of the up-counter 1 becoming "3", and a coincidence detection signal indicating that the two values coincide is outputted by the coincidence detector circuit 41.sub.B. As a result, a pulse T.sub.B is outputted from the pulse generator circuit 42.sub.B.

Similarly, the clock signal data D.sub.2 (d.sub.2) (="2") written in the third latch 3.sub.C are inputted to the third coincidence circuit 41.sub.C as data D.sub.C. Then, since an H level signal E.sub.C (=EN.sub.C) is supplied to the enable terminal EN of the third coincidence detector circuit 41.sub.C, operation of the coincidence circuit 41.sub.C is allowed, and a comparison is made between the count value N of the up-counter 1 and the clock number data D.sub.2 (d.sub.2) (="2"). Therefore, the generation of 2 clock signals .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in a coincidence detection signal being outputted by the coincidence detector circuit 41.sub.C. As a result, a pulse T.sub.C is outputted from the pulse generator circuit 42.sub.C.

Additionally, the clock signal data D.sub.2 (d.sub.1) (="1") written in the fourth latch 3.sub.D are inputted to the fourth coincidence circuit 41.sub.D as data D.sub.D, while an H level signal E.sub.D (=EN.sub.D) is supplied to the enable terminal EN of the fourth coincidence detector circuit 41.sub.D. As a result, the coincidence circuit 41.sub.D makes a comparison between the count value N of the up-counter 1 and the clock number data D.sub.2 (d.sub.1) (="1"). Therefore, the generation of 1 clock signal .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in a coincidence detection signal being outputted by the coincidence detector circuit 41.sub.D. As a result, a pulse T.sub.D is outputted from the pulse generator circuit 42.sub.D.

The pulses generated in this way by the pulse generator circuits 42.sub.A .about.42.sub.D are multiplexed by the multiplexer 5, and outputted as a timing signal T.sub.OUT. Thus, the present circuit is capable of counting over three rate signal pulse intervals, i.e. over four rates, so that a pulse delay of 4 rates is possible.

�Second Embodiment!

Next, a second embodiment of the present invention will be explained.

FIG. 3 is a block diagram showing a timing generator circuit according to a second embodiment of the present invention, which is capable of delaying for up to 4 rates as with the first embodiment. In the drawing, reference numeral 1 denotes an up-counter, reference numeral 2 denotes a decoder, reference numeral 3 denotes a four-stage shift register, reference numeral 4 denotes a coincidence detector, reference numeral 5 denotes a multiplexer, reference numeral 6 denotes an adder, reference numeral 7 denotes a delay circuit and reference numeral 8 denotes a register. This timing generator circuit is inputted with a rate signal pulse T.sub.0 having an undefined period, and delay assignment data D.sub.0 which is synchronized therewith. The delay assignment data D.sub.0 is composed of rate number data D.sub.1 for assigning the number of rates to be delayed, and lock number data D.sub.2 for assigning the delay time within the rates.

The up-counter 1 receives a clock signal .phi..sub.0 of frequency f.sub.0 as a clock input and counts up. The delay circuit 7 delays the rate signal pulse T.sub.0, then outputs the rate pulse signal T.sub.0 to the register 8. The register 8 receives the count value N of the up-counter 1 as a data input, and the rate signal pulse T.sub.0 delayed by the delay circuit 7 as a clock input. By inputting a delayed clock signal in this way, a count value N of the up-counter 1 which has been counted up by the clock signal .phi..sub.0 is inputted to the register 8.

The decoder 2 is a circuit for decoding the rate number data D.sub.1 inputted to the timing generator circuit and outputting the result as signals EN.sub.A .about.EN.sub.D. In the present embodiment, the signals EN.sub.A .about.EN.sub.D each go to level H when the rate number data D.sub.1 are "0".about."3".

The shift register 3 receives data composed of the output signals EN.sub.A .about.EN.sub.D of the decoder 2 and the clock number data D.sub.2 as input data, and comprises four-staged latches 3.sub.A .about.3.sub.D having the rate signal pulse T.sub.0 as the clock. Of the data outputted from the latch 3.sub.A of the first stage, the portion corresponding to the signal EN.sub.A is outputted as the output signal E.sub.A of the shift register 3, and the portion corresponding to the clock number data D.sub.2 is outputted as data D.sub.A. Additionally, of the data outputted from the latch 3.sub.B of the second stage, the portion corresponding to the signal EN.sub.B is outputted as the output signal E.sub.B of the shift register 3, and the portion corresponding to the clock number data D.sub.2 is outputted as data D.sub.B. Similarly, the signals E.sub.C and data D.sub.C are outputted from the latch 3.sub.C of the third stage, and the signals E.sub.D and data D.sub.D are outputted from the latch 3.sub.D of the fourth stage.

The adder 6 has a quadruple-parallel structure, comprising adders 6.sub.A .about.6.sub.D. The adder 6.sub.A adds the data D.sub.A outputted from the shift register 3 and the output data of the register 8, and outputs the addition results. Similarly, the adder 6.sub.B adds the data D.sub.B and the output data of the register 8, the adder 6.sub.C adds the data D.sub.C and the output data of the register 8 and the adder 6.sub.D adds the data D.sub.D and the output data of the register 8, then the addition results are outputted.

The coincidence detector 4 has a quadruple-parallel structure, and comprises coincidence detector circuits 41.sub.A .about.41.sub.D having enable functions, and pulse generator circuits 42.sub.A .about.42.sub.D which are respectively connected in series therewith. The output signal E.sub.A of the shift register 3 is inputted to the enable input terminal EN of the coincidence detector 41.sub.A, the output data of the adder 6.sub.A is inputted to the first data input terminal A, and the output data N.sub.REG of the register 8 is inputted to the second data input terminal B. When the input signal level at the enable input terminal EN is at level H and the output data of the adder 6.sub.A corresponds with the output data N.sub.REG of the register 8, the output signal of the coincidence detector circuit 41.sub.A is created, in response to which a single pulse T.sub.A is generated from the pulse generator circuit 42.sub.A. The same occurs with the coincidence detector circuits 41.sub.B .about.41.sub.D and the pulse generator circuits 42.sub.B .about.42.sub.D. The multiplexer 5 multiplexes the pulses T.sub.A .about.T.sub.D which are outputted in parallel from the pulse generator circuits 42.sub.A .about.42.sub.D of the coincidence detector 4 into a single signal which is outputted as a timing signal T.sub.OUT.

FIG. 4 is a time chart showing the operations of a timing generator circuit according to a second embodiment of the present invention. Hereinbelow, the operations of the present embodiment will be explained with reference to this diagram.

First, a first rate signal pulse T.sub.0 (t.sub.1) and delay assignment data D.sub.0 (d.sub.1) for assigning the delay amount of "3 rates+1 clock period" is supplied to this timing generator circuit. In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (="3") assigning a delay of 3 rates and clock number data D.sub.2 (="1") assigning a delay of 1 clock period. The rate number data D.sub.1 (="3") is inputted to the decoder 2. As a result, only the signal EN.sub.D of the output signals EN.sub.A .about.EN.sub.D of the decoder 2 goes to level H, and the others become level L. Then, input data composed of these signals EN.sub.A .about.EN.sub.D and the clock number data D.sub.2 (="1") are written into the first latch 3.sub.A of the shift register 3 by means of the rate signal pulse T.sub.0 (t.sub.1). Additionally, the rate signal pulse T.sub.0 (t.sub.1) is supplied to the clock input terminal of the register 8 via the delay circuit 7. As a result, the count value "1" of the up-counter 1 at this point in time is stored in the register 8.

The clock signal data D.sub.2 (d.sub.1) (="1") written into the first latch 3.sub.A is supplied to the first adder 6.sub.A of the adder 6 as data D.sub.A, and the output data of this adder 6.sub.A is supplied to the coincidence circuit 41.sub.A. However, at that time, an L-level signal E.sub.A (=EN.sub.A) is supplied from the first latch 3.sub.A to the enable terminal EN of the first coincidence detector circuit 41.sub.A. Consequently, the operation of the coincidence detector circuit 41.sub.A is prohibited.

Next, a second rate signal pulse T.sub.0 (t.sub.2) is supplied along with delay assignment data D.sub.0 (d.sub.2) for assigning a delay of "2 rates+2 clock periods". In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (d.sub.2) (="2") assigning a delay of 2 rates and clock number data D.sub.2 (d.sub.2) (="2") assigning a delay of 2 clock periods. As a result of the rate number data D.sub.1 (d.sub.2) (="2") being supplied to the decoder 2, the signal EN.sub.C goes to level H. Then, due to the second rate signal pulse T.sub.0 (t.sub.2), the signal EN.sub.B (=L), signal EN.sub.C (=L), signal EN.sub.D (=H) and the clock number data D.sub.2 (d.sub.1) (="1") stored in the first latch 3.sub.A are shifted to the second latch 3.sub.B. Additionally, input data composed of these signals EN.sub.A .about.EN.sub.D (only EN.sub.C is at level H) and the clock number data D.sub.2 (d.sub.2) (="2") are written into the first latch 3.sub.A by means of the rate signal pulse T.sub.0 (t.sub.2). Additionally, the rate signal pulse T.sub.0 (t.sub.2) is supplied to the clock input terminal of the register 8 via the delay circuit 7. As a result, the count value "4" of the up-counter 1 at this point in time is stored in the register 8.

Then, the clock signal data D.sub.2 (d.sub.2) written into the first latch 3.sub.A is inputted as data D.sub.A to the adder 6.sub.A of the adder section 6, while an L-level signal E.sub.A (=EN.sub.A) is supplied to the enable terminal EN of the first coincidence detector circuit 41.sub.A. Consequently, the operation of the coincidence detector circuit 41.sub.A is prohibited. Additionally, the clock number data D.sub.2 (d.sub.1) shifted to the second latch 3.sub.B is inputted to the second adder 6.sub.B as data D.sub.B, and the output data of this adder 6.sub.B is inputted to the second coincidence circuit 41.sub.B, while an L-level signal E.sub.B (=EN.sub.B) is supplied to the enable terminal EN of the second coincidence detector circuit 41.sub.B. Consequently, the operation of the coincidence detector circuit 41.sub.B is also prohibited.

Next, a third rate signal pulse T.sub.0 (t.sub.3) is supplied along with delay assignment data D.sub.0 (d.sub.3) for assigning a delay of "1 rate+3 clock periods". In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (d.sub.3) (="1") assigning a delay of 1 rate and clock number data D.sub.2 (d.sub.3) (="3") assigning a delay of 3 clock periods. As a result of the rate number data D.sub.1 (d.sub.3) (="1") being supplied to the decoder 2, the signal EN.sub.B goes to level H. Then, due to the third rate signal pulse T.sub.0 (t.sub.3), signal EN.sub.C (=L), signal EN.sub.D (=H) and the clock number data D.sub.2 (d.sub.2) (="2") stored in the second latch 3.sub.B are shifted to the third latch 3.sub.C. Additionally, the signal EN.sub.B (=L), signal EN.sub.C (=H) , signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.2) (="2") stored in the first latch 3.sub.A are shifted to the second latch 3.sub.B. Furthermore, input data composed of the output signals EN.sub.A .about.EN.sub.D (only EN.sub.B is at level H) of the decoder 2 and the clock signal data D.sub.2 (d.sub.3) (="3") are written into the first latch 3.sub.A. Additionally, the rate signal pulse T.sub.0 (t.sub.3) is supplied to the clock input terminal of the register 8 via the delay circuit 7, and the count value "5" of the up-counter 1 at this time is stored in the register 8.

Then, the clock signal data D.sub.2 (d.sub.3) written into the first latch 3.sub.A is inputted as data D.sub.A to the first adder 6.sub.A of the adder section 6, while an L-level signal E.sub.A (=EN.sub.A) is supplied to the enable terminal EN of the first coincidence detector circuit 41.sub.A. Consequently, the operation of the coincidence detector circuit 41.sub.A is prohibited. Additionally, the clock number data D.sub.2 (d.sub.2) shifted to the second latch 3.sub.B is inputted to the second coincidence detector circuit 41.sub.B as data D.sub.B, while an L-level signal E.sub.B (=EN.sub.B) is supplied to the enable terminal EN of the second coincidence detector circuit 41.sub.B. Consequently, the operation of the coincidence detector circuit 41.sub.B is also prohibited. Furthermore, the clock number data D.sub.2 (d.sub.2) shifted to the third latch 3.sub.C is inputted to the third adder 6.sub.C as data D.sub.C, and the output data of this adder 6.sub.C is inputted to the third coincidence detector, while an L-level signal E.sub.C (=EN.sub.C) is supplied to the enable terminal EN of the third coincidence detector circuit 41.sub.C. Consequently, the operation of the coincidence detector circuit 41.sub.C is also prohibited.

Next, a fourth rate signal pulse T.sub.0 (t.sub.4) is supplied along with delay assignment data D.sub.0 (d.sub.4) for assigning a delay of "0 rates+4 clock periods". In this case, the delay assignment data D.sub.0 is composed of rate number data D.sub.1 (d.sub.4) (="0") assigning a delay of 0 rates and clock number data D.sub.2 (d.sub.4) (="4") assigning a delay of 4 clock periods. As a result of the rate number data D.sub.1 (d.sub.4) (="0") being supplied to the decoder 2, the signal EN.sub.A goes to level H. Then, due to the fourth rate signal pulse T.sub.0 (t.sub.4), the signal EN.sub.D (=H) and the clock signal data D.sub.2 (d.sub.1) (="1") are shifted to the fourth latch 3.sub.D. Additionally, the signal EN.sub.C (=H), signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.2) (="2") stored in the second latch 3.sub.B are shifted to the third latch 3.sub.C. Additionally, the signal EN.sub.B (=H), signal EN.sub.C (=L), signal EN.sub.D (=L) and the clock number data D.sub.2 (d.sub.3) (="3") stored in the first latch 3.sub.A are shifted to the second latch 3.sub.B. Furthermore, input data composed of the output signals EN.sub.A .about.EN.sub.D (only EN.sub.A is at level H) of the decoder 2 and the clock signal data D.sub.2 (d.sub.4) (="4") are written into the first latch 3.sub.A. Additionally, the rate signal pulse T.sub.0 (t.sub.4) is supplied to the clock input terminal of the register 8 via the delay circuit 7, and the count value "7" of the up-counter 1 at this time is stored in the register 8.

The clock signal data D.sub.2 (d.sub.4) (="4") written in the first latch 3.sub.A are supplied as data D.sub.A to the first adder 6.sub.A of the adder section 6, and added to the output data N.sub.REG (="7") of the register 8. Consequently, the addition result "11" is outputted from the adder 6.sub.A, and inputted to the first coincidence detector circuit 41.sub.A. Then, since an H level signal E.sub.A (=EN.sub.A) is supplied to the enable terminal EN of the first coincidence detector circuit 41.sub.A, operation of the coincidence circuit 41.sub.A is allowed, and a comparison is made between the count value N of the up-counter 1 and the addition result "11" of the adder 6.sub.A. Therefore, the generation of 4 clock signals .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in the count value N of the up-counter 1 becoming "11", and a coincidence detection signal indicating that the two values coincide is outputted by the coincidence detector circuit 41.sub.A. As a result, a pulse T.sub.A is outputted from the pulse generator circuit 42.sub.A.

On the other hand, the clock signal data D.sub.2 (d.sub.3) (="3") written in the second latch 3.sub.B are supplied as data D.sub.B to the second adder 6.sub.B of the adder section 6, and added to the output data N.sub.REG (="7") of the register 8. Consequently, the addition result "10" is outputted from the adder 6.sub.B, and inputted to the second coincidence detector circuit 41.sub.B. Then, since an H level signal E.sub.B (=EN.sub.B) is supplied to the enable terminal EN of the second coincidence detector circuit 41.sub.B, operation of the coincidence circuit 41.sub.B is allowed, and a comparison is made between the count value N of the up-counter 1 and the addition result "10" of the adder 6.sub.B. Therefore, the generation of 3 clock signals .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in the count value N of the up-counter 1 becoming "10", and a coincidence detection signal indicating that the two values coincide is outputted by the coincidence detector circuit 41.sub.B. As a result, a pulse T.sub.B is outputted from the pulse generator circuit 42.sub.B.

Similarly, the clock signal data D.sub.2 (d.sub.2) (="2") written in the third latch 3.sub.C are supplied as data D.sub.C to the third adder 6.sub.C of the adder section 6, and added to the output data N.sub.REG (="7") of the register 8. Consequently, the addition result "9" is outputted from the adder 6.sub.C, and inputted to the third coincidence detector circuit 41.sub.C. Then, since an H level signal E.sub.C (=EN.sub.C) is supplied to the enable terminal EN of the third coincidence detector circuit 41.sub.C, operation of the coincidence circuit 41.sub.C is allowed, and a comparison is made between the count value N of the up-counter 1 and the addition result "9" of the adder 6.sub.C. Therefore, the generation of 2 clock signals .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in a coincidence detection signal being outputted by the coincidence detector circuit 41.sub.C. As a result, a pulse T.sub.C is outputted from the pulse generator circuit 42.sub.C.

Additionally, the clock signal data D.sub.2 (d.sub.1) (="1") written in the fourth latch 3.sub.D are supplied as data D.sub.D to the fourth adder 6.sub.D of the adder section 6, and added to the output data N.sub.REG (="7") of the register 8. Consequently, the addition result "8" is outputted from the adder 6.sub.D, and inputted to the fourth coincidence detector circuit 41.sub.D. At this time, an H level signal E.sub.D (=EN.sub.D) is supplied to the enable terminal EN of the fourth coincidence detector circuit 41.sub.D. As a result, the coincidence circuit 41.sub.D makes a comparison between the count value N of the up-counter 1 and the addition result "8" of the adder 6.sub.D. Therefore, the generation of 1 clock signal .phi..sub.0 after the input of the rate signal pulse T.sub.0 (t.sub.4) results in a coincidence detection signal being outputted by the coincidence detector circuit 41.sub.D, As a result, a pulse T.sub.D is outputted from the pulse generator circuit 42.sub.D.

The pulses generated in this way by the pulse generator circuits 42.sub.A .about.42.sub.D are multiplexed by the multiplexer 5, and outputted as a timing signal T.sub.OUT. Thus, the present circuit is capable of counting over three rate signal pulse intervals, i.e. over four rates, so that a pulse delay of 4 rates is possible.

While the explanation of timing generator circuits according to the first embodiment and the second embodiment of the present invention as given above used examples wherein the maximum delay assignment value was 4 rates, the same operations are possible for maximum delay assignment values of n rates if the decoder 2, the shift register 3 and the coincidence detector section 4 are expanded.

Claims

1. A timing generator circuit for receiving rate signal pulses and delay assignment data composed of rate number data and clock number data, and outputting timing signals delayed from the input timing of the rate signal pulses by intervals corresponding to said delay assignment data comprising;

a counter for counting clock signals, which is reset by means of said rate signal pulses;

a shift register for sequentially shifting said delay assignment data by means of said rate signal pulses;

a coincidence detector section for detecting data corresponding to said rate number data from among output data from each stage of said shift register, and outputting pulses when said clock number data contained in said output data coincide with count values of said counter; and

a multiplexer section for multiplexing the pulses outputted from said coincidence detector section and outputting the result as said timing signals.

2. A timing generator circuit in accordance with claim 1, having an input terminal for said rate number data and a plurality of output terminals, and a decoder in between said input terminal and said shift register for decoding the rate number data inputted from said input terminal and outputting the results from said plurality of output terminals to said shift register.

3. A timing generator circuit for receiving rate signal pulses and delay assignment data composed of rate number data and clock number data, and outputting timing signals delayed from the input timing of the rate signal pulses by intervals corresponding to said delay assignment data, comprising;

a counter for counting clock signals;

a shift register for sequentially shifting said delay assignment data by means of said rate signal pulses;

a register for storing count values of said counter when said rate signal pulses are received;

an adder section for adding data corresponding to said clock number data contained in output data from each stage of said shift register with the count values stored in said register, and outputting the addition results;

a coincidence detector section for detecting data corresponding to said rate number data from among said output data from each stage of said shift register, and outputting pulses when the addition results of said adder section coincide with count values of said counter; and

a multiplexer section for multiplexing the pulses outputted from said coincidence detector section and outputting the result as said timing signals.

4. A timing generator circuit in accordance with claim 3, having an input terminal for said rate number data and a plurality of output terminals, and a decoder in between said input terminal and said shift register for decoding the rate number data inputted from said input terminal and outputting the results from said plurality of output terminals to said shift register.