Patent Application
20240105793
The description herein relates to the field of integrated circuit (IC) field effect transistor (FET) designs, and more particularly to FETs designed with reduced leakage.
In the fabrication of integrated circuit (IC) field effect transistors (FET), silicon-on-insulator (SOI) substrates, rather than over bulk silicon substrates, may be used since SOI substrates results in higher speed, lower power consumption, improved radio frequency (RF) performance, and improved radiation resistance. FETs may have different voltage domains and logic that operate between a wide range of voltages.
Embodiments of the present disclosure provide devices, apparatuses, and methods related to FETs with reduced leakage. In some embodiments, devices on a silicon-on-insulator substrate may include a silicon layer; a gate structure at least partially overlaying the silicon layer; and an oxide layer disposed between the partial overlay of the gate structure and the silicon layer, wherein: the oxide layer comprises a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlay.
In some embodiments, methods of forming a device on a silicon-on-insulator substrate may include providing a silicon layer; providing an oxide layer; and providing a gate structure at least partially overlaying the silicon layer, wherein: the oxide layer is disposed between the partial overlay of the gate structure and the silicon layer; the oxide layer comprises a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer in the partial overlay.
In some embodiments, silicon-on-insulator substrates may include a silicon layer; an oxide layer for receiving a portion of a gate structure, wherein: the oxide layer comprises a first portion and a second portion; the first portion of the oxide layer is thicker than the second portion of the oxide layer; and the first portion of the oxide layer covers at least a portion of a first edge of the silicon layer.
In some embodiments, devices on a silicon-on-insulator substrate may include a silicon island formed in a silicon layer; a first gate structure formed in an active region on the silicon island, the first gate structure comprising a first gate oxide layer with a first gate oxide layer thickness; and a second gate structure and a third gate structure each formed over an edge of the silicon island and each extending from the first gate structure, the second gate structure comprising a second gate oxide layer with a second gate oxide layer thickness and the third gate structure comprising a third gate oxide layer with a third gate oxide layer thickness, wherein the first gate oxide layer thickness is less than the second gate oxide layer thickness and less than the third gate oxide layer thickness.
In some embodiments, methods of forming a device on a silicon-on-insulator substrate may include providing a silicon layer; providing an active region in the silicon layer; providing a first gate oxide layer over at least one portion of a central region of the active region; providing a second gate oxide layer over at least one edge of the active region; providing a conductive gate material over the first gate oxide layer and the second gate oxide layer; and forming a gate structure overlaying the active region in the silicon layer, wherein: the gate structure extends across the active region, covering at least two edges and the at least one portion of the central region; and the first gate oxide layer is thinner than the second gate oxide layer.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations consistent with the disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the subject matter recited in the appended claims. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments.
As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.
Devices with SOI substrates may use thin silicon for better switch performance, but thin silicon suffers from constraints in that it tends to reduce the threshold voltage of a device, thereby increasing current leakage. These effects increase towards edge regions of the thin silicon, where the thin silicon forms a “tip” (also known as a “bird's beak”) that is shaped by oxidation or a shallow trench isolation (STI) process during fabrication and is especially thin. This tip of the thin silicon has an especially low threshold voltage, thereby increasing current leakage of a device often called “edge leakage”. In some cases, the threshold voltage of a tip of thin silicon may be as low as zero volts (V). The thickness of the thin silicon may also be reduced due to an oxygen diffusion path at the edge of and underneath the thin silicon. This oxygen diffusion may cause or form the tip or bird's beak of thin silicon. Moreover, the thickness of the thin silicon may be further reduced due to oxidation of the thin silicon from the gate oxide, thereby reducing the threshold voltage and increasing current leakage.
FETs may suffer from performance constraints if any current leakage occurs during operation of a device. For example, increased current leakage may increase the power consumption of a device. Therefore, a solution that satisfies the speed and current leakage requirements for transistors that operate over a wide range of voltages is needed to address the long-felt need of reduced current leakage in SOI, including, for example, radio frequency silicon-on-insulator (RFSOI) technology, and complementary metal oxide semiconductor (CMOS) transistors (e.g., bulk CMOS transistors).
These devices may be fabricated with thicker gate oxides to improve switch performance. However, using thicker gate oxides also suffers from drawbacks in that it degrades transistors. Moreover, oxidation from the gate oxide still reduces the thickness of the thin silicon. For example, in n-channel MOSFETs (NMOSFETs), the oxidation process that reduces the thickness of the thin silicon layer may deplete the dopants in the thin silicon, thereby further reducing the threshold voltage. The dopant depletion in the thin silicon reduces the threshold voltage due to the band gap at the edge regions of the thin silicon being bent downward. In p-channel MOSFETs (PMOSFETs), the oxidation process may further thin the thin silicon, thereby reducing the threshold voltage.
In some cases, the threshold voltage may be adjusted to help suppress current leakage by adjusting the doping type and dopant concentration under the gate. However, adjusting the doping type has some constraints in that a thick gate oxide may be used to reduce current leakage from the adjusted doping, but a device with a thin gate oxide may not be able to operate under the required voltage. Moreover, while using a thin gate oxide increases the drive current in a transistor, it also results in a faster increase in capacitance, thereby reducing the speed of the transistor.
In some cases, digital logic using transistors may use flared gates to increase the effective channel length at edge regions of the active thin silicon. However, flared gates increase the capacitance of a device, thereby reducing logic speed. Moreover, flared gates may be used in devices with thinner gate oxides in a dual-gate process, which further reduces logic speed due to the thinner oxide increasing capacitance.
Embodiments of the present disclosure provide devices, apparatuses, and methods that reduce current leakage and operate between a wide range of voltages at a high speed by providing a device (e.g., with an SOI substrate) with an increased threshold voltage. For example, some embodiments include a device with two dual-gate regions and an active region between the two dual-gate regions. In some embodiments, the gate oxide in the active region is thinner than the gate oxide in the dual-gate regions. The gate oxide may be thicker in the dual-gate regions since each dual-gate region may include edge regions of the silicon layer that are more susceptible to current leakage.
Some of the figures of this disclosure described below show NMOSFETs. However, the teachings of the invention may be applicable to PMOSFETs in some applications. Accordingly, the illustrated embodiments and example materials should not be taken as limitations on the scope of the invention. In some embodiments, to describe embodiments of the invention, a polysilicon gate structure and an oxide gate insulator may be used as an example, but other gate materials may be used to implement the invention.
Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described.
In some embodiments, transistor 100 may include a first dual-gate region 102, a second dual-gate region 106, and a region 104 between first dual-gate region 102 and second dual-gate region 106. For example, region 104 may be an active region that is between dual-gate region 102 and dual-gate region 106 (e.g., region 104 is outside of dual-gate region 102 and outside of dual-gate region 106). In some embodiments, an island of active silicon layer 112 may be formed on an SOI substrate. A gate structure 108 including an insulator (e.g., an oxide layer) and overlaying gate material (e.g., polysilicon, conductive material, etc.) may be formed at least partially over silicon layer 112 (e.g., gate structure 108 may at least partially overlay silicon layer 112). In some embodiments, silicon layer 112 may include one or more contacts 114. In some embodiments, transistor 100 may include P+ implant region 132, N+ implant region 134 that overlaps silicon layer 112, and P+ implant region 136.
In some embodiments, silicon layer 112 may be a thin silicon layer to improve switch performance. In some embodiments, an oxide layer may be disposed between the overlay of gate structure 108 and silicon layer 112.
For illustrative purposes, a cross-sectional view of silicon layer 112 and the oxide layer along A-A′ is provided in
In order to increase the threshold voltage and reduce the current leakage of a transistor, a first portion 142 of an oxide layer in a dual-gate region may be thicker than a second portion 144 of the oxide layer in an active region. First portion 142 of the oxide layer may be thicker in dual-gate regions since each dual-gate region may include edges of silicon layer 112 that are more susceptible to current leakage, as described above. Since higher conduction may be needed in an active region and there is reduced drive current in the active region, second portion 144 of the oxide layer may be thinner in the active region. In some embodiments, second portion 144 of the oxide layer may cover at least a portion of silicon layer 112 in the partial overlay of gate structure 108. In some embodiments, second portion 144 of the oxide layer may cover an entirety of silicon layer 112 in region 104.
First portion 142 of the oxide layer in the dual-gate regions may also increase the threshold voltage in tip 122a of silicon layer 112 that is formed in the edges of silicon layer 112. That is, first portion 142 of the oxide layer may be formed on tip 122a of silicon layer 112, thereby making tips 122 more robust to oxide breakdown and reducing current leakage at tip 122a. Therefore, first portion 142 of the oxide layer may be configured to reduce current leakage in edge transistors of a transistor.
In some embodiments, the partial overlay of gate structure 108 and silicon layer 112 may include a first edge and a second edge of silicon layer 112 in the at least partial overlay of gate structure 108. In some embodiments, first portion 142 of the oxide layer may cover at least a portion of the first edge of silicon layer 112. In some embodiments, first portion 142 of the oxide layer may cover an entirety of silicon layer 112 in dual-gate region 102 (e.g., first portion 142 of the oxide layer may cover silicon layer 112 in dual-gate region 102 where gate structure 108 at least partially overlays silicon layer 112 and where gate structure 108 does not overlay silicon layer 112). In some embodiments, first portion 142 of the oxide layer, the first edge of silicon layer 112, and the portion of gate structure 108 on the first edge of silicon layer 112 may define edge transistor 110.
In some embodiments, the oxide layer may include a third portion 146, similar to first portion 142, that may cover at least a portion of the second edge of silicon layer 112. Similar to portion 112a of silicon layer 112, a thickness of a portion 112c of silicon layer 112 at an edge of silicon layer 112 in a dual-gate region (e.g., dual-gate region 106 or dual-gate region 102 of
Third portion 146 of the oxide layer in the dual-gate regions may also increase the threshold voltage in tip 122c of silicon layer 112 that is formed in the edges of silicon layer 112. That is, third portion 146 of the oxide layer may be formed on tip 122c of silicon layer 112, thereby making tip 122c more robust to oxide breakdown and reducing current leakage at tip 122c. Therefore, third portion 146 of the oxide layer may be configured to reduce current leakage in edge transistors of a transistor.
In some embodiments, third portion 146 of the oxide layer may cover an entirety of silicon layer 112 in dual-gate region 106 (e.g., the third portion of the oxide layer may cover silicon layer 112 in dual-gate region 106 where gate structure 108 at least partially overlays silicon layer 112 and where gate structure 108 does not overlay silicon layer 112). In some embodiments, third portion 146 of the oxide layer, the second edge of silicon layer 112, and the portion of gate structure 108 on the second edge of silicon layer 112 may define an edge transistor 120. That is, for purposes of this disclosure, edge transistors 110 and 120 may be indicated by bold lines in
In some embodiments, the dopant concentration in implant region 134 in active region 104 may be higher than implant regions 132 and 136 in dual-gate regions 102 and 106 so that the threshold voltage in all regions may be high, thereby reducing current leakage.
In some SOI processes, a device may have the same well for thin oxide regions and thick oxide regions, but different LDDs and halos for the thin oxide regions and thick oxide regions. In some embodiments consistent with the current disclosure, different wells may be used for thin oxide regions and thick oxide regions, but the same LDDs and halos may be used in the thin oxide regions and thick oxide regions. In some embodiments, when the well doping of a thin oxide region is much higher than the well doping of a thick oxide region, the thick oxide region may have a higher threshold voltage at edge regions to reduce current leakage. In some embodiments, the threshold voltage and current leakage at edge regions may depend on the amount of well doping and the thickness of the oxide (e.g., high well doping and thicker oxide may increase the threshold voltage at edge regions to reduce current leakage).
Embodiments where the same LDDs and halos are formed in the thin oxide region and in the thick oxide region may be advantageous since the only major process adjustment is adjusting the oxide thickness. These embodiments may also be advantageous in that it avoids misalignment that can sometimes occur when different LDDs and halos are formed in the thin oxide region and the thick oxide region.
In some embodiments, transistor 300 may include a first dual-gate region 302, a second dual-gate region 306, and a region 304 between first dual-gate region 302 and second dual-gate region 306. For example, region 304 may be an active region that is between dual-gate region 302 and dual-gate region 306 (e.g., region 304 is outside of dual-gate region 302 and outside of dual-gate region 306). In some embodiments, an active silicon layer 312 may be formed on an SOI substrate. A gate structure 308 including an insulator (e.g., an oxide layer) and overlaying gate material (e.g., polysilicon, conductive material, etc.) may be formed at least partially over silicon layer 312 (e.g., gate structure 308 may at least partially overlay silicon layer 312). In some embodiments, silicon layer 312 may include one or more contacts 314. In some embodiments, P+ implant region 332, N+ implant region 334, and P+ implant region 336 may overlap silicon layer 312.
In some embodiments, silicon layer 312 may be a thin silicon that results in improved switch performance. In some embodiments, an oxide layer may be disposed between the overlay of gate structure 308 and silicon layer 312.
In some embodiments, the at least partial overlay of gate structure 308 and silicon layer 312 may include a first edge, a second edge, a third edge, and a fourth edge of silicon layer 312 in the at least partial overlay of gate structure 308. In some embodiments, a first portion (e.g., first portion 142 of
In some embodiments, the oxide layer may include a third portion (e.g., third portion 146 of
In order to increase the threshold voltage and reduce the current leakage of a transistor, a first portion the oxide layer in dual-gate regions 302 and 306 may be thicker than a second portion of the oxide layer (e.g., second portion 144 of
The first portion of the oxide layer in dual-gate regions 302 and 306 may also increase the threshold voltage in the tips (e.g., tips 122a or 122c of
In some embodiments, gate structure 308 may be modified to increase or “flare” the effective channel length of edge transistors 310, 311, 320, and 321 relative to the length of the central conduction channel of transistor 300 (e.g., gate structure 308 may be flared in dual-gate region 302 and in dual-gate region 306). The increased edge transistor channel length results in a further reduction of leakage current. While the flared shape of gate structure 308 increases its capacitance, thereby reducing logic speed, the thick portions of the oxide layer under the flared portions of gate structure 308 reduces the capacitance of gate structure 308, thereby increasing logic speed.
In some embodiments, silicon layer 312 may be body-tied (e.g., rather than a floating body like silicon layer 112 of
In some SOI processes, a device may have the same well for thin oxide regions and thick oxide regions, but different LDDs and halos for the thin oxide regions and thick oxide regions. In some embodiments consistent with the current disclosure, different wells may be used for thin oxide regions and thick oxide regions, but the same LDDs and halos may be used in the thin oxide regions and thick oxide regions. Since the well doping of a thin oxide region is much higher than the well doping of a thick oxide region, the thick oxide region will have a higher threshold voltage at edge regions to reduce current leakage.
Embodiments where the same LDDs and halos are formed in the thin oxide region and in the thick oxide region may be advantageous since the only major process adjustment is adjusting the oxide thickness. These embodiments may also be advantageous in that it avoids misalignment that can sometimes occur when different LDDs and halos are formed in the thin oxide region and the thick oxide region.
At step 401, a silicon layer (e.g., silicon layer 112 of
At step 403, an oxide layer may be provided. In some embodiments, the oxide layer may be disposed between the at least partial overlay of the gate structure and the silicon layer. In some embodiments, the at least partial overlay may include a first region (e.g., dual-gate region 102 of
In some embodiments, the first portion of the oxide layer may cover an entirety of the silicon layer in the first region (e.g., the first portion of the oxide layer may cover the silicon layer in a dual-gate region where the gate structure at least partially overlays the silicon layer and where the gate structure does not overlay the silicon layer). In some embodiments, the oxide layer may include a third portion, similar to the first portion, that may cover at least a portion of a third edge and a fourth edge of the silicon layer. In some embodiments, the third portion of the oxide layer may cover an entirety of the silicon layer in a third region (e.g., the third portion of the oxide layer may cover the silicon layer in a dual-gate region where the gate structure at least partially overlays the silicon layer and where the gate structure does not overlay the silicon layer). In some embodiments, the third portion of the oxide layer, the third edge and/or the fourth edge of the silicon layer, and the portion of the gate structure on the third edge and/or the fourth edge of the silicon layer may define edge transistor(s) (e.g., edge transistors 310, 311, 320, or 321 of
In order to increase the threshold voltage and reduce the current leakage of a transistor, the first portion and the third portion of the oxide layer in the dual-gate regions may be thicker than a second portion of the oxide layer in the active region. The first portion and the third portion of the oxide layer may be thicker in the dual-gate regions since each dual-gate region may include edges of the silicon layer that are more susceptible to current leakage, as described above. Since higher conduction may be needed in an active region and there is no drive current in the active region, the second portion of the oxide layer may be thinner in the active region. In some embodiments, the second portion of the oxide layer may cover at least a portion of the silicon layer in the at least partial overlay of the gate structure. In some embodiments, the second portion of the oxide layer may cover an entirety of the silicon layer in the active region.
The first portion and the third portion of the oxide layer in the dual-gate regions may also increase the threshold voltage in the tips (e.g., tips 122a or 122c of
At step 405, a gate structure (e.g., gate structure 108 of
The embodiments may further be described using the following clauses:
It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof.
Fabrication Technologies & Options
The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.
With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions have been greatly exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.
Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form part of an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.
Some or all aspects of the invention may be implemented in hardware or software, or a combination of both (e.g., programmable logic arrays). Unless otherwise specified, the methods included as part of the invention are not inherently related to any particular computer or other apparatus. In particular, various general purpose computing machines may be used with programs written in accordance with the teachings herein, or it may be more convenient to use a special purpose computer or special-purpose hardware (such as integrated circuits) to perform particular functions. Thus, embodiments of the invention may be implemented in one or more computer programs (i.e., a set of instructions or codes) executing on one or more programmed or programmable computer systems (which may be of various architectures, such as distributed, client/server, or grid) each comprising at least one processor, at least one data storage system (which may include volatile and non-volatile memory and/or storage elements), at least one input device or port, and at least one output device or port. Program instructions or code are applied to input data to perform the functions described herein and generate output information. The output information is applied to one or more output devices, in known fashion.
Each such computer program may be implemented in any desired computer language (including machine, assembly, or high level procedural, logical, object oriented programming languages or a custom language/script) to communicate with a computer system, and may be implemented in a distributed manner in which different parts of the computation specified by the software are performed by different processors. In any case, the computer language may be a compiled or interpreted language. Computer programs implementing some or all of the invention may form one or more modules of a larger program or system of programs. Some or all of the elements of the computer program can be implemented as data structures stored in a computer readable medium or other organized data conforming to a data model stored in a data repository.
Each such computer program may be stored on or downloaded to (for example, by being encoded in a propagated signal and delivered over a communication medium such as a network) a tangible, non-transitory storage media or device (e.g., solid state memory media or devices, or magnetic or optical media) for a period of time (e.g., the time between refresh periods of a dynamic memory device, such as a dynamic RAM, or semi-permanently, or permanently), the storage media or device being readable by a general or special purpose programmable computer for configuring and operating the computer when the storage media or device is read by the computer system to perform the procedures described above. The inventive system may also be considered to be implemented as a non-transitory computer-readable storage medium, configured with a computer program, where the storage medium so configured causes a computer system to operate in a specific or predefined manner to perform the functions described above.
