Claims
- 1. A method for forming trenches in a device layer disposed on a silicon semiconductor substrate, said method comprising:
covering the device layer with an etch resistant masking layer to define at least two trench regions; removing semiconductor material from the exposed trench regions by applying an etching agent that selectively etches the semiconductor substrate with respect to the trench masking layer, thereby forming at least two trenches each comprising a floor and sidewalls; and during said removing of semiconductor material, exposing said sidewalls to a passivating agent in increasing amounts with time, thereby passivating said sidewalls while reducing lateral etching of semiconductor material from said sidewalls.
- 2. The method of claim 1 wherein said etching agent is selected from the group consisting of chlorine, sulfur hexafluoride, and nitrogen trifluoride.
- 3. The method of claim 1 wherein said passivating agent is selected from the group consisting of oxygen, oxygen-containing compounds, hydrogen bromide, helium, and mixtures thereof.
- 4. The method of claim 1 wherein said etching agent is sulfur hexafluoride and said passivating agent is oxygen.
- 5. The method of claim 1 wherein the amount of passivating agent is increased in discrete steps comprising substantially equal time intervals.
- 6. The method of claim 1 wherein the amount of passivating agent is increased in discrete steps comprising controlled time intervals of varying duration.
- 7. The method of claim 1 wherein said trenches comprise isolation trenches or gate trenches for a QVDMOS device.
- 8. The method of claim 1 wherein said trenches have a pitch of 1.5 μm or more.
- 9. The method of claim 1 wherein said etching further comprises isotropic plasma etching of an upper portion of said trenches.
- 10. The method of claim 1 wherein said etch resistant masking layer is formed by chemical vapor deposition.
- 11. The method of claim 1 wherein said etch resistant masking layer comprises deposited organic material.
- 12. The method of claim 1 wherein said etch resistant masking layer is selected from the group of materials consisting of low temperature oxide, CVD oxide, thermally grown oxide, CVD nitride, oxynitride, borophosphosilicate glass, a photosensitive material, a polyimide, and a photoresist.
- 13. The method of claim 12 wherein said etch resistant masking layer is formed from low temperature oxide.
- 14. The method of claim 1 wherein said trenches surround an island that includes one or more semiconductor devices.
- 15. The method of claim 14 further comprising: forming source regions at the surface adjacent said trenches, a channel region adjacent trenches and below said source regions, a buried highly doped layer beneath said trenches, and conductive via from said buried layer to said surface.
- 16. The method of claim 1 further comprising: coating said semiconductor material in said trenches with a gate insulating layer, then depositing conductive material over said gate insulating layer, thereby forming trench gates.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application, which is a continuation-in-part of U.S. application Ser. No. 09/797,323, filed Mar. 1, 2001, claims the benefit of U.S. Provisional Application Serial No. 60/234,563, filed Sep. 22, 2000.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60234563 |
Sep 2000 |
US |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
09797323 |
Mar 2001 |
US |
Child |
09956568 |
Sep 2001 |
US |