TRENCH ISOLATION STRUCTURE HAVING DIFFERENT STRESS

Abstract

By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of an appropriate mask layer, which may provide a patterned optical response for a lamp-based or laser-based anneal process. Consequently, the intrinsic stress of isolation trenches may be specifically adapted to the requirements of circuit elements, such as N-channel transistors and P-channel transistors.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1e schematically show cross-sectional views of a semiconductor structure containing a conventional isolation trench during various manufacturing stages;

FIGS. 2 a-2e schematically show cross-sectional views of an isolation structure having two different isolation trenches with different intrinsic stress due to different annealing conditions in accordance with illustrative embodiments of the present invention; and

FIGS. 3 a-3c schematically show cross-sectional views of an isolation structure having a plurality of isolation trenches each of which is treated with different annealing conditions in accordance with still other illustrative embodiments of the present invention.

Claims

1. A method, comprising: forming a first isolation trench and a second isolation trench in a semiconductor layer, said first and second isolation trenches being filled with an insulating material; andheat treating said first and second isolation trenches for generating a first stress in said first isolation trench and a second stress in said second isolation trench, said first stress being different from said second stress.

2. The method of claim 1, wherein heat treating said first and second isolation trenches comprises annealing said first isolation trench with a first temperature and annealing said second isolation trench with a second temperature other than said first temperature.

3. The method of claim 2, wherein annealing said first and second isolation trenches with a first and second temperature, respectively, comprises forming a mask layer to cover said first isolation trench and expose said second isolation trench and applying a heat generating radiation.

4. The method of claim 3, wherein said mask layer is configured to absorb a substantial amount of energy contained in said heat generating radiation.

5. The method of claim 3, wherein said mask layer is configured to reflect a substantial amount of energy contained in said heat generating radiation.

6. The method of claim 1, wherein heat treating said first and second isolation trenches comprises heat treating at least one of said first and second isolation trenches in an oxidizing ambient.

7. The method of claim 1, further comprising forming a thermal oxide on oxidizable inner surface portions of said first and second isolation trenches and filling said first and second isolation trenches with an insulating material.

8. The method of claim 1, wherein heat treating said first and second isolation trenches comprises commonly heating said first and second isolation trenches by a furnace process.

9. The method of claim 8, wherein heat treating said first and second isolation trenches further comprises annealing said first and second isolation trenches with at least one of a different temperature and a different duration.

10. The method of claim 8, wherein heat treating said first and second isolation trenches further comprises annealing said first and second isolation trenches with at least one of a different temperature and a different duration prior to said furnace process.

11. The method of claim 3, further comprising filling said first and second isolation trenches with said insulating material and removing excess material prior to forming said mask layer.

12. The method of claim 11, further comprising forming an etch stop layer above said first and second isolation trenches after removing said excess material and forming said mask layer above said etch stop layer.

13. The method of claim 1, wherein heat treating said first and second isolation trenches comprises modifying at least one characteristic of a material located above said first and second isolation trenches and irradiating said first and second isolation trenches through said material located above said first and second isolation trenches.

14. The method of claim 13, wherein said material located above said first and second isolation trenches is an excess portion of said insulating material.

15. The method of claim 13, wherein said material above said first and second isolation trenches is deposited after filling said first and second isolation trenches with said insulating material and removing excess portion of said insulating material.

16. The method of claim 13, wherein modifying at least one characteristic of said material comprises selectively implanting an ion species in said material.

17. The method of claim 1, further comprising forming a P-channel field effect transistor adjacent to said first isolation trench, wherein said first isolation trench has a compressive stress.

18. The method of claim 17, further comprising forming an N-channel field effect transistor adjacent to said second isolation trench, said second isolation trench having a compressive stress less than said first isolation trench.

19. A semiconductor device, comprising: a first isolation trench filled with an insulating material and having a first intrinsic stress; anda second isolation trench filled with said insulating material and having a second intrinsic stress other than said first intrinsic stress.

20. The semiconductor device of claim 19, further comprising a P-channel field effect transistor formed adjacent to said first isolation trench and an N-channel transistor formed adjacent to said second isolation trench, said first isolation trench having a compressive stress that is higher than a compressive stress of said second isolation trench.