Patent Application
20230043402
The present invention relates to a trench-type MESFET.
Ga2O3-based trench MOSFETs with a gate electrode buried in a semiconductor layer are known (see, e.g., Patent Literature 1). A trench MOSFET has high withstand voltage characteristics due to the trench gate-structure thereof.
In MOSFETs, resistance of the semiconductor layer and withstand voltage characteristics are generally correlated. Increasing resistance of the semiconductor layer can improve withstand voltage characteristics but causes an increase in conduction losses. Compared to planar MOSFETs, trench MOSFETs can easily achieve both high withstand voltage and low loss since the trench gate-structure thereof improves withstand voltage characteristics without increasing resistance of the semiconductor layer.
Patent Literature 1: JP 2016/15503 A
However, the trench MOSFET disclosed in Patent Literature 1 cannot operate at very high frequencies and cannot be used for applications that require to operate at high frequencies, such as applications in cell phone base station equipment or wireless power feeding equipment.
It is an object of the invention to provide a trench-type MESFET that can be driven at high frequency while having a high withstand voltage.
To achieve the above object, one aspect of the invention provides a trench-type MESFET defined by (1) to (5) below.
According to the invention, it is possible to provide a trench-type MESFET that can be driven at high frequency while having a high withstand voltage.
The trench-type MESFET 1 includes an n-type semiconductor substrate 10, an n-type semiconductor layer 11 that is a layer stacked on the n-type semiconductor substrate 10 and has plural trenches 12 opening on a surface 19 on the opposite side to the n-type semiconductor substrate 10, first insulators 14 respectively buried in bottom portions of the plural trenches 12, gate electrodes 13 respectively buried in the plural trenches 12 so as to be placed on the first insulators 14 and so that side surfaces thereof are in contact with the n-type semiconductor layer 11, a source electrode 16 connected to mesa-shaped portions 18 between adjacent trenches 12 of the n-type semiconductor layer 11, and a drain electrode 17 formed on a surface of the n-type semiconductor substrate 10 on the opposite side to the n-type semiconductor layer 11.
Depletion layers are formed in the mesa-shaped portions 18 of the n-type semiconductor layer 11 due to Schottky barriers formed at interfaces between the n-type semiconductor layer 11 and the gate electrodes 13. In the trench-type MESFET 1, it is possible to control a thickness of the depletion layer by gate voltage (voltage applied to the gate electrodes 13, or voltage applied between the source electrode and the gate electrodes 13 when the source electrode 16 is grounded), and thereby possible to open/close channels in the mesa-shaped portions 18.
The trench-type MESFET 1 may be either of a normally-off type or a normally-on type, but is usually manufactured to be of the normally-off type in view of safety when used as a power device. It is to prevent conduction between the source electrode 16 and the drain electrode 17 in the event that the gate becomes uncontrollable due to wire breakage, etc., in a gate circuit.
In the normally-off trench-type MESFET 1, the channels in the mesa-shaped portions 18 are closed by the depletion layers in a state in which gate voltage is not applied. Then, by applying a gate voltage of not less than the threshold voltage, the depletion layers become thin, the channels open, and current flows from the drain electrode 17 to the source electrode 16.
The n-type semiconductor substrate 10 is formed of an n-type Ga2O3-based single crystal containing a group IV element such as Si or Sn as a donor. A donor concentration in the n-type semiconductor substrate 10 is, e.g., not less than 1.0×1018cm-3 and not more than 1.0×1020cm-3. A thickness of the n-type semiconductor substrate 10 is, e.g., not less than 10 µm and not more than 600 µm.
The Ga2O3-based single crystal here means a Ga2O3 single crystal or is a Ga2O3 single crystal doped with an element such as Al or In, and may be, e.g., a (GaxAlyIn(1-x-y))2O3 (0<x≤1, 0≤y<1, 0<x+y≤1) single crystal which is a Ga2O3 single crystal doped with Al and In. The band gap is widened by adding Al and is narrowed by adding In. The Ga2O3 single crystal mentioned above has, e.g., a β-crystal structure.
A plane orientation of the n-type semiconductor substrate 10 is not specifically limited, but is preferably a (001) plane on which a Ga2O3-based single crystal constituting the n-type semiconductor layer 11 is formed at a high growth rate, or it is also preferably a (011) plane on which a Ga2O3-based single crystal film with a flat surface can be grown.
The n-type semiconductor layer 11 is formed of an n-type Ga2O3-based single crystal containing a group IV element such as Si or Sn as a donor. A thickness T of the n-type semiconductor layer 11 is, e.g., not less than 1 µm and not more than 500 µm.
The n-type semiconductor layer 11 has a channel layer 11b in which the gate electrodes 13 are buried and channels are formed when gate voltage is applied, a withstand voltage layer 11a provided under the channel layer 11b to maintain withstand voltage, and a contact layer 11c formed in the vicinity of an interface with the source electrode 16 by ion implantation or epitaxial growth, etc., to provide an ohmic connection between the source electrode 16 and the n-type semiconductor layer 11.
Here, a region of the n-type semiconductor layer 11 located below (on the drain electrode 17 side of) the height of the bottoms of the trenches 12, i.e., a region between the bottoms of the trenches 12 and a bottom surface 20 (a surface on the drain electrode 17 side) of the n-type semiconductor layer 11 is the withstand voltage layer 11a and a thickness thereof is defined as Tp. A region of the n-type semiconductor layer 11 located above (on the source electrode 16 side of) the height of the bottoms of the trenches 12 is the channel layer 11b, and the contact layer 11c is provided in the vicinity of the upper end of the channel layer 11b.
A donor concentration in the withstand voltage layer 11a is one of the parameters determining the breakdown characteristics of the trench-type MESFET 1, and given that breakdown field strength of Ga2O3 stays constant at 8 MV/cm, it is preferably not more than about 3×1017 cm-3 to obtain withstand voltage of 600 V, not more than about 1.5×1017 cm-3 to obtain withstand voltage of 1200 V, not more than about 5.4×1016 cm-3 to obtain withstand voltage of 3300 V, not more than about 2.7×1016 cm-3 to obtain withstand voltage of 6600 V, not more than about 1.5×1016 cm-3 to obtain withstand voltage of 12000 V, and not more than about 2×1015 cm-3 to obtain withstand voltage of 100000 V. To obtain withstand voltage of less than 600 V or withstand voltage of more than 6600 V, the concentration is respectively set to appropriate values. In addition, when the maximum breakdown field strength of Ga2O3 is about 4 MV/cm, the concentrations are respectively not more than half of the above-mentioned values.
The thickness Tp of the withstand voltage layer 11a is one of parameters determining the breakdown characteristics of the trench-type MESFET 1, and given that breakdown field strength of Ga2O3 stays constant at 8 MV/cm which is a value estimated from the band gap, the thickness Tp needs to be, e.g., at least not less than about 1 to 2 µm to obtain performance of having withstand voltage of 600V used for home appliances or in-vehicle devices, etc., not less than about 3 µm to obtain withstand voltage of 1200 V used for industrial equipment, etc., not less than about 8 to 9 µm to obtain withstand voltage of 3300 V used for large transportation equipment such as bullet train, etc., not less than about 16 to 17 µm to obtain withstand voltage of 6600 V in high power applications such as power generation and transmission, etc., not less than about 30 µm to obtain withstand voltage of 12000 V in medium-voltage circuit breakers, and not less than about 250 µm to obtain withstand voltage of 100000 V in high-voltage circuit breakers.
The maximum breakdown field strength of Ga2O3 has not been able to be actually measured at the moment, and if it is about 4 MV/cm which is the largest of the actually measured values, the film thicknesses mentioned above need to be doubled. For example, about 500 µm is required to obtain withstand voltage of 100000 V. To obtain withstand voltage of less than 600 V for small home appliances, the thickness Tp may be less than 1 µm but is preferably about 1 µm at minimum in view of production stability. Thus, the thickness Tp is preferably not less than 1 µm and not more than 500 µm.
A channel concentration in the channel layer 11b (a donor concentration in a region between two adjacent gate electrodes 13) and a mesa width Wm, which is a width of the mesa-shaped portion 18, are one of the parameters determining whether the trench-type MESFET 1 is of the normally-off type or the normally-on type, and the channel concentration and the mesa width Wm should be reduced to form the normally-off type, and the donor concentration and the mesa width Wm should be increased to form the normally-on type.
To suppress an off leakage current in the trench-type MESFET 1 when it is of the normally-off type, it is preferable that, e.g., the mesa width Wm be not more than 0.4 µm when a work function of the gate electrode 13 is 4.5 eV and the channel concentration in the channel layer 11b is from 5×1015 cm-3 to 1×1016 cm-3, the mesa width Wm be not more than 0.6 µm when the work function of the gate electrode 13 is 5.0 eV and the channel concentration in the channel layer 11b is not more than 5×1015 cm-3, the mesa width Wm be not more than 0.4 µm when the work function of the gate electrode 13 is 5.0 eV and the channel concentration in the channel layer 11b is more than 5×1015 cm-3 and not more than 1×1016 cm-3, and the mesa width Wm be not more than 0.6 µm when the work function of the gate electrode 13 is from 5.5 to 6.5 eV and the channel concentration in the channel layer 11b is from 5×1015 cm-3 to 1×1016 cm-3.
When the width Wm of the mesa-shaped regions is smaller, the channel concentration can be higher and on-resistance of the channel layer 11b can be thus reduced. However, when the width Wm is smaller, there is a problem that it is more difficult to manufacture and this causes a decrease in production yield.
For this reason, when the trenches 12 are formed by, e.g., patterning using a general stepper, the width Wm of the mesa-shaped regions is preferably not less than 0.5 µm and not more than 2 µm, and when the trenches 12 are formed by patterning using EB (electron beam) lithography with higher resolution, the width Wm of the mesa-shaped regions is preferably not less than 0.1 µm and not more than 2 µm.
A width Wt of the trench 12 also depends on the resolution of an exposure system and is thus preferably set within a numerical range similar to the width Wm of the mesa-shaped regions according to the type of the exposure system to be used.
A thickness of the contact layer 11c is, e.g., not less than 10 nm and not more than 5 µm. A donor concentration in the contact layer 11c is higher than the channel concentration in the channel layer 11b and is, e.g., not less than 1×1018 cm-3 and not more than 1×1021 cm-3.
The gate electrode 13 is formed of a material with which the channels in the mesa-shaped portions 18 can be opened/closed by applying a gate voltage within the range not causing gate leakage. When, e.g., NiO is used as a material of the gate electrode 13, applying a gate voltage within the range not causing gate leakage allows a wide range of current to flow from the drain electrode 17 to the source electrode 16 in the normally-off trench-type MESFET 1.
The insulators 14 are buried in the bottom portions of the trenches 12 and are located between the gate electrodes 13 and the withstand voltage layer 11a. Insulators 15 are buried in the trenches 12 so as to be placed on the gate electrodes 13 and are located between the gate electrodes 13 and the source electrode 16. The insulators 14 and the insulators 15 are formed of, e.g., HfO2 or SiO2.
The n-type semiconductor layer 11 is formed of, e.g., an epitaxially grown film formed by the HVPE method, etc. When the n-type semiconductor layer 11 is formed by the HVPE method, a chloride gas is used as a source material for Ga2O3-based single crystal or a dopant source material. Therefore, the n-type semiconductor layer 11 contains Cl derived from the source material for Ga2O3-based single crystal or the dopant source material.
When using the HVPE method, it is possible to reduce film formation time and the cost since the crystal growth rate is high. This feature is advantageous particularly when forming a thick n-type semiconductor layer 11. In addition, when using the HVPE method, it is possible to form the n-type semiconductor layer 11 with good crystal quality and thus possible to improve the production yield. Furthermore, since it is possible to form the n-type semiconductor layer 11 with high purity, it is possible to highly accurately control the donor concentration.
The contact layer 11c may be formed by implanting a donor, using an ion implantation process, into an upper portion of the channel layer 11b formed by epitaxial growth, but the manufacturing cost can be kept low when the Ga2O3-based single crystal is formed by crystal growth while adding a donor impurity.
The source electrode 16 is formed on the upper surface 19 of the n-type semiconductor layer 11 and is connected to the mesa-shaped portions 18. The drain electrode 17 is connected to a surface of the n-type semiconductor substrate 10 on the opposite side to the n-type semiconductor layer 11 as shown in
The source electrode 16 and the drain electrode 17 are respectively ohmic-connected to the contact layer 11c of the n-type semiconductor layer 11 and to the n-type semiconductor substrate 10. The source electrode 16 and the drain electrode 17 have, e.g., a Ti/Au stacked structure.
Electric field intensity at a point P1 in the channel layer 11b in the vicinity of an edge 130 (an end in a direction of the width Wt) of a bottom portion of the gate electrode 13 and electric field intensity at a point P2 on an edge (an end in the direction of the width Wt) of an upper portion of the insulator 14 depend on a curvature radius R at an apex of a curve at the edge 130 of the bottom portion of the gate electrode 13 in a cross section in a width direction of the trench 12 (the direction of the width Wt) shown in
When the vicinity of the apex of the curve at the edge 130 of the bottom portion of the gate electrode 13 in the cross section in the width direction of the trench 12 is approximated to a circular arc, a circle C shown in
By keeping electric field intensity low at the point P1 in the channel layer 11b and at the point P2 in the insulator 14 which are at the end portion of the gate electrode 13, it is possible to suppress gate leakage over a Schottky barrier formed at an interface between the channel layer 11b and the gate electrode 13.
To prevent gate leakage in, e.g., the normally-off trench-type MESFET 1 at the time of applying a voltage of 1200 V between the source electrode 16 and the drain electrode 17, a value of the curvature radius R is preferably not less than 0.1 µm.
Meanwhile, electric field intensity at a point P3 in the withstand voltage layer 11a in the vicinity of the center of the bottom portion of the trench 12 in the direction of the width Wt and electric field intensity at a point P4 in the insulator 14 in the vicinity of the center of the bottom portion of the trench 12 in the direction of the width Wt depend on the donor concentration in the withstand voltage layer 11a and a thickness Ti of the insulator 14.
By keeping electric field intensity low at the point P3 in the withstand voltage layer 11a and at the point P4 in the insulator 14 which are points with particularly high electric field intensity in the n-type semiconductor layer 11 and the insulator 14, it is possible to suppress dielectric breakdown of the n-type semiconductor layer 11 and the insulator 14.
To prevent dielectric breakdown of the n-type semiconductor layer 11 and the insulator 14 in, e.g., the normally-off trench-type MESFET 1 at the time of applying a voltage of 1200 V between the source electrode 16 and the drain electrode 17, the donor concentration in the withstand voltage layer 11a is preferably not more than 7×1016 cm-3 and the thickness Ti of the insulator 14 is preferably in a range of not less than 50 nm and not more than 300 nm.
The insulators 14 and the insulators 15 are formed by, e.g., the atomic layer deposition (ALD) method. It is possible to control the shape of the edge of the upper portion of the insulator 14 by the formation conditions, etc., of the insulator 14, and thereby possible to control the curvature radius R of the gate electrode 13.
In the trench-type MESFET 1 in the above embodiment, high withstand voltage can be achieved by the trench structure and high-frequency driving can be achieved by the MESFET structure.
Current-voltage characteristics of the trench-type MESFET 1 in the embodiment described above were investigated by simulation. In this simulation, the electron affinity of the n-type semiconductor layer 11 was set to 3.7 eV assuming that the material thereof is Ga2O3, and the potential of the source electrode 16 was set to 0 V.
According to
As a result of research to find a more suitable material as the material of the gate electrode 13, the inventor found that NiO is suitable as the material of the gate electrode 13.
The n-type Ga2O3 film 52 and the p-type NiO film 53 form a pn junction, and the pn junction diode 50 uses rectifying characteristics of this pn junction.
In the pn junction diode 50, a potential barrier at an interface between the p-type NiO film 53 and the n-type Ga2O3 film 52 as viewed from the n-type Ga2O3 film 52 is lowered by applying forward voltage between the anode electrode 54 and the cathode electrode 55 (positive potential on the anode electrode 54 side), allowing a current to flow from the anode electrode 54 to the cathode electrode 55.
The n-type Ga2O3 substrate 51 is formed of an n-type Ga2O3 single crystal containing Sn as a donor impurity. A donor concentration in the n-type Ga2O3 substrate 51 is about 1.0×1018 cm-3. A thickness of the n-type Ga2O3 substrate 51 is about 600 µm.
The n-type Ga2O3 film 52 is formed of an n-type Ga2O3 single crystal containing Si as a donor impurity. A donor concentration in the n-type Ga2O3 film 52 is 6×1016 cm-3. A thickness of the n-type Ga2O3 film 52 is about 3 µm.
The p-type NiO film 53 is formed of p-type NiO.
The anode electrode 54 is composed of a circular Ni film with a diameter of 300 µm and forms an ohmic junction with the p-type NiO film 53.
The cathode electrode 55 is composed of a Ti/Au film and forms an ohmic junction with the n-type Ga2O3 substrate 51.
According to
From the upper limit of the gate voltage which can be applied to the gate electrode 13 while suppressing occurrence of gate leakage and the range of drain current which can be passed while suppressing occurrence of gate leakage, it was confirmed that NiO is a more preferable material for the gate electrode 13 than Pt.
Although the material (base crystal) of the n-type semiconductor layer 11 was a Ga2O3 single crystal in the simulation of Example 1, similar results are obtained also when simulating with other Ga2O3-based single crystals.
For the trench-type MESFET 1 in the embodiment described above, a relationship between the curvature radius R at the apex of the curve at the edge 130 of the bottom portion of the gate electrode 13 in the cross section in the width direction of the trench 12 and electric field intensity at the point P1 in the channel layer 11b and at the point P2 in the insulator 14 (see
In this simulation, the electron affinity of the n-type semiconductor layer 11 was set to 3.7 eV, the thickness Tp of the withstand voltage layer 11a was set to 4.3 µm, the width Wm of the mesa-shaped portion 18 was set to 0.4 µm, the channel concentration in the channel layer 11b was set to 1×1016 cm-3, the donor concentration in the withstand voltage layer 11a was set to 9×1016 cm-3, a dielectric constant of the insulator 14 was set to 22, the thickness Ti of the insulator 14 was set to 0.2 µm, the work function of the gate electrode 13 was set to 5.0 eV, the potentials of the source electrode 16 and the gate electrode 13 were set to 0 V, and the potential of the drain electrode 17 was set to 1200 V. In this regard, the electron affinity of 3.7 eV for the n-type semiconductor layer 11 is based on the assumption that the material thereof is Ga2O3, the work function of 5.0 eV for gate electrode 13 is based on the assumption that the material thereof is Pt, and the dielectric constant of 22 for the insulator 14 is based on the assumption that the material thereof is HfO2.
To suppress the gate leakage over the Schottky barrier formed at the interface between the channel layer 11b and the gate electrode 13, electric field intensity at the point P1 in the channel layer 11b is preferably not more than 2.5 MV/cm (a dashed line in
According to
Although the material (base crystal) of the n-type semiconductor layer 11 was a Ga2O3 single crystal in the simulation of Example 2, similar results are obtained also when simulating with other Ga2O3-based single crystals. In addition, although the material of the insulator 14 was HfO2, similar results are obtained also when simulating with SiO2.
For the trench-type MESFET 1 in the embodiment described above, a relationship between the donor concentration in the withstand voltage layer 11a and electric field intensity at the point P3 in the withstand voltage layer 11a and at the point P4 in the insulator 14 was investigated by simulation.
In this simulation, the electron affinity of the n-type semiconductor layer 11 was set to 3.7 eV, the thickness Tp of the withstand voltage layer 11a was set to 7 µm, the width Wm of the mesa-shaped portion 18 was set to 0.4 µm, the channel concentration in the channel layer 11b was set to 1×1016 cm-3, the dielectric constant of the insulator 14 was set to 22, the thickness Ti of the insulator 14 was set to 0.2 µm, the work function of the gate electrode 13 was set to 5.0 eV, the curvature radius R of the gate electrode 13 was set to 0.2 µm, the potentials of the source electrode 16 and the gate electrode 13 were set to 0 V, and the potential of the drain electrode 17 was set to 1200 V. In this regard, the electron affinity of 3.7 eV for the n-type semiconductor layer 11 is based on the assumption that the material thereof is Ga2O3, the work function of 5.0 eV for gate electrode 13 is based on the assumption that the material thereof is Pt, and the dielectric constant of 22 for the insulator 14 is based on the assumption that the material thereof is HfO2.
To suppress dielectric breakdown of the n-type semiconductor layer 11 and the insulator 14, electric field intensity at the point P3 in the withstand voltage layer 11a is preferably not more than 8 MV/cm (a dashed line in
According to
Although the material (base crystal) of the n-type semiconductor layer 11 was a Ga2O3 single crystal in the simulation of Example 3, similar results are obtained also when simulating with other Ga2O3-based single crystals. In addition, although the material of the insulator 14 was HfO2, similar results are obtained also when simulating with SiO2.
For the trench-type MESFET 1 in the embodiment described above, a relationship between the thickness Ti of the insulator 14 and electric field intensity at the point P3 in the withstand voltage layer 11a and at the point P4 in the insulator 14 was investigated by simulation.
In this simulation, the electron affinity of the n-type semiconductor layer 11 was set to 3.7 eV, the thickness Tp of the withstand voltage layer 11a was set to 4.4 µm, the width Wm of the mesa-shaped portion 18 was set to 0.4 µm, the channel concentration in the channel layer 11b was set to 1×1016 cm-3, the dielectric constant of the insulator 14 was set to 22, the work function of the gate electrode 13 was set to 5.0 eV, the curvature radius R of the gate electrode 13 was set to 0.2 µm, the potentials of the source electrode 16 and the gate electrode 13 were set to 0 V, and the potential of the drain electrode 17 was set to 1200 V. In this regard, the electron affinity of 3.7 eV for the n-type semiconductor layer 11 is based on the assumption that the material thereof is Ga2O3, the work function of 5.0 eV for gate electrode 13 is based on the assumption that the material thereof is Pt, and the dielectric constant of 22 for the insulator 14 is based on the assumption that the material thereof is HfO2.
As described above, to suppress dielectric breakdown of the n-type semiconductor layer 11 and the insulator 14, electric field intensity at the point P3 in the withstand voltage layer 11a is preferably not more than 8 MV/cm (a dashed line in
According to
Although the material (base crystal) of the n-type semiconductor layer 11 was a Ga2O3 single crystal in the simulation of Example 4, similar results are obtained also when simulating with other Ga2O3-based single crystals. In addition, although the material of the insulator 14 was HfO2, similar results are obtained also when simulating with SiO2.
Although the embodiments and Examples of the invention have been described, the invention is not intended to be limited to the embodiments and Examples, and the various kinds of modifications can be implemented without departing from the gist of the invention.
In addition, the invention according to claims is not to be limited to the embodiments and Examples described above. Further, it should be noted that not all combinations of the features described in the embodiments and Examples are necessary to solve the problem of the invention.
Provided is a trench-type MESFET that has a high withstand voltage and can be driven at high frequency.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-234981 | Dec 2019 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2020/046717 | 12/15/2020 | WO |
