This application is a division of application Ser. No. 08/290,323, filed Aug. 15, 1994 now abandoned. This application is related to commonly owned U.S. Pat. No. 5,316,959, entitled "Trenched DMOS Transistor Fabrication Using Six Masks", inventors Sze-Hon Kwan et al. issued May 31, 1994.
Number | Name | Date | Kind |
---|---|---|---|
4567641 | Baliga et al. | Feb 1986 | |
4941026 | Temple | Jul 1990 | |
4954854 | Dhong et al. | Sep 1990 | |
5019526 | Yamane et al. | May 1991 | |
5072266 | Bulucea et al. | Dec 1991 | |
5168331 | Yilmaz | Dec 1992 | |
5304831 | Yilmaz et al. | Apr 1994 | |
5316959 | Kwan et al. | May 1994 | |
5341011 | Hshieh et al. | Aug 1994 | |
5430324 | Bencuya | Jul 1995 | |
5482888 | Hsu et al. | Jan 1996 | |
5534454 | Tsuzuki et al. | Jul 1996 |
Number | Date | Country |
---|---|---|
0345380 | Dec 1989 | EPX |
2647596 | May 1990 | FRX |
3932621 | Sep 1989 | DEX |
56-58267 | May 1981 | JPX |
59-84474 | May 1984 | JPX |
62-176168 | Aug 1987 | JPX |
1-42177 | Feb 1989 | JPX |
1-198076 | Aug 1989 | JPX |
1-310576 | Dec 1989 | JPX |
2-91976 | Mar 1990 | JPX |
Entry |
---|
Barbuscia, et al., IEDM, 1984, pp. 757-760 "Modeling of Polysilicon Dopant Diffusion for Shallow-Junction Bipolar Technology". |
S.C. Sun et al., pp. 356-367, IEEE Trans, Electron Devices, vol. ED-27, Feb. 1980 "Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power Transistors". |
Chang et al., et al. "Vertical FET Random-Access Memories with Deep Trench Isolation", IBM Technical Disc. Bulletin, vo. 22, No. 8B, Jan. 1980, pp. 3683-3687. |
P. Ou-Yang, "Double Ion Implanted V-MOS Technology", IEEE Journal of Solid State Circuits, vol. SC-12, No. 1, Feb. 1977, pp. 3-8. |
K. Shenai, et al., International Electron Devices Meeting, 9 Dec. 1990, San Francisco, USA, pp. 793-797. |
Number | Date | Country | |
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Parent | 290323 | Aug 1994 |