This disclosure relates generally to MMICs having capacitors with different capacitances.
As is known in the art, it is sometimes desirable to provide a plurality of different capacitors having different capacitances on a common surface of a substrate providing a Monolithic Microwave Integrated Circuit (MMIC).
In accordance with the disclosure, a structure is provided, comprising: a body; a pair of capacitors disposed over different portions of a surface of the body; a first one of the capacitors having an upper conductor and a lower conductor separated by a dielectric layer; and a second one of the pair of capacitors having an upper conductor and a lower conductor separated a dielectric structure, the dielectric structure having a lower dielectric layer, and an upper dielectric layer, wherein the material. of the lower dielectric layer being different from the material of the upper dielectric layer.
The use of different dielectric materials within the metal-insulator-metal (MIM) capacitor dielectric of a MMIC results in lower MMIC cost, higher reliability and higher performance.
In one embodiment, a method is provided for forming a plurality of metal-insulator-metal (MIM) capacitors on a surface of a body, the capacitors having different insulator dielectric thicknesses. The method includes: forming a plurality of lower metal conductors over the surface of the body, each one of the conductors providing a lower electrode for a corresponding one of the capacitors; depositing a first dielectric layer over the surface of the body, portions of the first dielectric layer being disposed over the plurality of lower conductors; depositing a second dielectric layer over the first dielectric layer including the portions of the first dielectric disposed over the plurality of lower conductors; forming a mask over the second dielectric layer, such mask having a window therein exposing a first portion of the second dielectric layer disposed over a first one of the lower metal conductors while covering a second portion of the second dielectric layer over a second one of the lower metal conductors; exposing the mask to an etch, the etch having a etch rate in the second dielectric layer being greater than the etch rate in the first dielectric layer, the etch removing the second dielectric layer exposed by the window exposing an underlying portion of the first dielectric layer while leaving the underlying portion of the first dielectric layer over the first one of the lower metal conductors; removing the mask exposing both the second dielectric layer over a second one of the lower metal conductors and the underlying portion of the first dielectric layer over the first one of the lower metal conductors; depositing an upper metal layer over the exposed second portion of the second dielectric layer over a second one of the lower metal conductors and the underlying portion of the first dielectric layer over the first one of the lower metal conductors; and patterning the upper metal layer to form an upper electrode for a first one of the capacitors over the first one of the lower electrodes and an upper electrode for a second one of the capacitors.
With such an arrangement, a capacitor dielectric stack-up is provided with an etch stop layer (the first dielectric layer) allows design flexibility to remove or not remove the top dielectric layer and change the total thickness.
The layer thicknesses of the dielectric layers can be Chosen so that a capacitor having both layers can withstand the highest DC plus voltage within the MMIC thereby eliminating the need for multiple capacitors in series. If the upper dielectric layer is etched away to leave only the lower dielectric layer, the lower dielectric layer thickness can be chosen so that it has an adequate breakdown rating for DC bypassing with a smaller area.
The method can be used to eliminate air bridges: When it is required to have a signal cross another conductor on a without being connected, rather than using an air bridge; the upper metal therein when used with high power may sometimes degrade due to the temperature rise caused by the high RF or DC current levels. By eliminating the air bridge as a cross-over in accordance with the disclosure, a cross-over in accordance with the disclosure has a much better heat path than an air bridge so it will be much less prone to failure while still being able to withstand high RF or DC voltage levels without breakdown.
In one embodiment, the method includes; forming an additional lower conductor over the surface of the body. Portions of the first dielectric layer are also deposited over the additional lower conductor; portions of the second dielectric layer are deposited over the portions of the first dielectric layer over the additional lower conductor; portions of the mask are deposited over a portion of the second insulating layer over the additional lower metal conductors; portions of the upper metal layer are disposed over the second dielectric layer above the additional lower metal conductor. The patterning of the upper metal layer forms a conductor crossing over the additional lower conductor.
In one embodiment, the thick top dielectric layer over a Field Effect Transistor (FM) region is etched away to eliminate its additional dielectric loading on the FET performance. Therefore the above benefits for capacitors and air bridge elimination can be achieved with little or no performance impact to the PETs. The added flexibility to choose the thicknesses of the two dielectric layers could also be used to even improve the FET performance.
The details of one or more embodiments of the disclosure are set forth. in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.
Referring now to
More particularly, referring now to
Next, lower conductors 40, 42 and 44 are formed on the first dielectric layer 34 over the high voltage capacitor region 20, the low voltage capacitor region 24, and the cross-over region 28 using conventional photolithographic processing, for example. Next, a second. dielectric layer 46 (
Next, a mask 48 is formed on the surface of the MMIC, the mask having windows 50 over the source and drain contacts 30, 32, as shown. The portions of the second dielectric layer 46 exposed by the windows 50 are etched away using conventional lithographic etching techniques, for example, to expose the source 30 and drain 32.
Next, the mask 48 is removed leaving the structure shown in
Next, a field plate 52 (
Next, a dielectric etch stop layer 54 (
Next, a mask. 58 is formed on the surface of the structure, the mask 58 having windows 60, 62 exposing the FBI region 16 and the low voltage capacitor region 24 but remaining over the high voltage capacitor region 20 and the cross over region 28, as shown in
Next, a new mask 64 (
Next, the mask 64 is removed. A conductor is deposited over the surface of the structure and patterned into the upper conductors 70a for the source electrode, the drain electrode 70b, the high voltage capacitor 70d, the low voltage capacitor 70c and the cross over conductor 700 using conventional photolithographic-etching techniques, for example, producing the MMIC 12 shown in
A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, a two dielectric structure may be formed, by eliminating etch stop layer 54 and making the lower dielectric layer 46 from the same dielectric material that had been used for the etch stop layer 54. The thickness of the lower dielectric layer 46 is chosen to meet the capacitance and breakdown voltage requirements for capacitor 22 (