Patent Application
20090053834
The present invention relates generally to semiconductor devices and more particularly to methods of using scatterometry for in-line detection of polysilicon strings left in STI divots after the gate etching process in the fabrication of integrated circuits.
In the fabrication of semiconductor devices, isolation structures are formed between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The isolation structures, for example, shallow trench isolation (STI) structures, are typically formed during initial processing of a semiconductor substrate, prior to the formation of such electrical devices.
A MOSFET transistor is a basic building block in a CMOS device, for example, wherein the transistor can be controlled to operate either in a digital or analog manner. In the fabrication of MOSFET transistors, source and drain regions are doped opposite that of a body region or well region in a semiconductor substrate. During the manufacture of shallow trench isolation, divots in the silicon oxide fill are often unintentionally formed. The divots have a divot width, a divot length, and a divot depth, for example. The divots and subsequent deposited polysilicon left within the divots can significantly change MOSFET performance.
The divots and their characterization become even more important as the semiconductor devices further shrink in size. As polysilicon is layered over MOSFET active areas and the oxide fills, for example, the polysilicon when forming a gate will wrap over the actives and fill the divot. The transistors are then no longer the transistors that were designed because of the polysilicon left in the divot changes the MOSFETs performance. Polysilicon strings left after a gate etch in STI divots is a very common defect which can cause electrical shorts between gates, for example.
There are current techniques to measure the divot characteristics; however they are destructive, for example requiring the potting and cross sectioning of the device, which leaves the device inoperable. These techniques are utilized when a problem has already been discovered; at the end stages of workpiece processing, in other words, after many expensive processing acts have been completed, increasing the cost of a failed workpiece. Currently there is no in-line, non-destructive control of the workpiece processing with respect to divot characterization and divot correction.
Therefore a need exists in the semiconductor industry for an improved method to perform divot characterization and divot correction utilizing an in-line process and doing so in a non-destructive manner.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key nor critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One embodiment is a method of forming an integrated circuit, comprising, forming an STI structure in a semiconductor body, the STI structure having a divot characteristic, performing scatterometry on the STI structure and obtaining signature spectra associated therewith and continuing fabrication of the integrated circuit when the obtained signature spectra satisfies a predetermined performance specification.
Another embodiment is a method of utilizing scatterometry to obtain STI divot data on a semiconductor device in process, comprising creating or simulating a plurality of periodic STI structures, measuring or simulating STI divot data for each of the plurality of periodic STI structures, performing or simulating scatterometry on each of the plurality of periodic STI structures to obtain signature spectra on each of the plurality of periodic STI structures, storing the signature spectra of each of the plurality of periodic STI structures and the associated measured or simulated STI divot data, for each of the plurality of periodic STI structures in an electronic library, performing scatterometry on the semiconductor device in process and collecting resultant signature spectra associated therewith and comparing semiconductor device in process signature spectra to the signature spectra of each of the plurality of periodic STI structures in the electronic library and determining the closest match as an indication of the semiconductor device in process STI divot data.
In yet another embodiment, is a method of detection of polysilicon strings left in STI divots, comprising creating or simulating two dimensional model structures to mimic actual process conditions, performing or simulating two dimensional scatterometry on the two dimensional model structures to obtain database empirical or simulated signature spectra, storing the entire database signature spectra in an electronic library, performing two dimensional scatterometry on an in-process semiconductor device to obtain a device signature spectra, comparing the device signature spectra to the database signature spectra, and taking corrective action on the in-process semiconductor device if unacceptable polysilicon stringers are detected, otherwise continuing with the processing of the in-process semiconductor device.
Yet another embodiment involves a method of detection of polysilicon strings left in STI divots, comprising performing scatterometry on an actual two dimensional in-process semiconductor device to obtain a device signature spectrum, comparing the device signature spectra to empirical or simulated spectra indicating polysilicon, and taking corrective action on the in-process semiconductor device if an unacceptable level of polysilicon is detected, otherwise continuing with the processing of the in-process semiconductor device.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
The present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The drawings are not drawn to scale, nor are individual components within the drawings necessarily drawn in scale relative to one another. However, the method is applicable to other processes, for example, a process for forming any suitable digital or analog electronic device, for example, switches, I/O devices, logic devices, analog devices, power IC outputs, switches, inverter switches, and the like that form polysilicon stringers during their manufacture. Furthermore, while the following detailed description is presently contemplated by the inventor for practicing the invention, it should be understood that the description of this embodiment is merely illustrative and that it should not be taken in a limiting sense.
As device sizes shrink, it becomes more and more important to prevent and/or deal with work piece defects in a suitable and efficient manner. One type of defect that the inventor has appreciated is divots formed within an STI. These divots can retain and hold polysilicon that becomes polysilicon strings in a subsequent processing. These polysilicon strings: can cause device failure, unexpected performance, having to discard work pieces, etc.
In order to fully appreciate the various aspects of the present invention, a brief description of at least one embodiment of a semiconductor device including an STI region will be discussed. In the fabrication of semiconductor devices, isolation structures are: formed between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The isolation structures, in this case STI structures, are typically formed during initial processing of a semiconductor substrate, prior to the formation of such electrical devices.
Many companies employ STI technology to isolate electronic devices (e.g., transistors) on an integrated circuit in order to prevent current leakage between the various devices. STI has replaced the traditional LOCOS (local oxidation of silicon) structures, in some applications due to STI providing a more controlled form of electrical isolation. LOCOS structures, in contrast, typically consume larger amounts of space because the oxidation region expands the isolation area laterally in proportion to the depth of the isolation.
While the methods herein are illustrated and described as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated acts may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the operation of devices which are illustrated and described herein (e.g., device 10 in
A MOSFET transistor is a basic building block in a CMOS device, for example, wherein the transistor can be controlled, to operate either in a digital or analog manner. In the fabrication of MOSFET transistors, source and drain regions are doped opposite that of a body region or well region in a semiconductor substrate.
As illustrated in
Referring to
As illustrated in
The divots 36 are even more important as the semiconductor devices further shrink in size. As polysilicon (not shown) is layered over the oxide fill 38, for example, the polysilicon when forming a gate will wrap over the active and the oxide fill 38 and fill or partially fill the divot 36. The subsequently formed transistor is then no longer the transistor that was designed/intended because of the polysilicon left in the divot 36. Polysilicon strings are often left after gate etch, for example, in STI divots and this common defect can cause electrical shorts between gates. This becomes more critical as the devices are reduced in size, as discussed supra because the divot 36 becomes a larger contributing factor to errors in the semiconductor device.
Now referring to
Referring to
The process begins at 402 of
At 408 each of the periodic STI structures with the signature spectrum obtained empirically or by simulation can have its characteristic divot data measured or simulated using common destructive testing or analysis, for example. The periodic STI structure can be potted in epoxy and cross sectioned using standard techniques and then TEM can be used to determine the divot length, divot width and divot depth, for example. At 410 the measured or simulated characteristic divot data and the signature spectra associated with the divot data, for each of the periodic STI structures, can be stored in an electronic library as an associated data set (e.g., data set (1): signature spectrum for periodic STI structure (1), pivot characteristics for periodic STI structure (1)). It is to be understood that the electronic library comprises raw data, STI divot data, signature spectra for the periodic STI structures, signature spectra for empirical or simulated devices, indexing data, software, hardware, and the like. Again there can be hundreds or thousands of these data sets in the library that associate a specific signature spectra, empirical or simulated with a measured set of STI divot data.
At 412, scatterometry is performed on the semiconductor device going through a given process. The scatterometry can be performed on an intermittent or a continual basis, depending on the process underway.
At 414, the semiconductor device signature spectrum is compared to the electronic library of signature spectra and the closest match is automatically determined, as an indication of the STI divot characteristics (e.g., STI divot width, STI divot depth, surface roughness, etc.). It is to be appreciated that various sorting and optimization techniques can be employed determining the closest match and all such techniques are contemplated herein. At 414, an operator (of an actual fabrication process) can determine if the STI divot is too large or an in-line process automatically determines if the divot characteristic measurements are out of specification, for example. If the divot characteristics are out of an acceptable range (i.e., unacceptable), corrective action can be taken at 418, otherwise the process continues at 420, as illustrated. If the corrective action is performed at 418 then the process can again continue at 420. The corrective actions may include additional processing to remove or reduce the divot, discarding the device, and the like.
Referring to
The divots 36 and the remaining polysilicon 44 are an even more important defect as the semiconductor devices further shrink in size. As polysilicon is layered over the active 34 and the oxide fill 38, for example, the polysilicon when forming a gate (not shown) will wrap over the active 34 (and the oxide fill 38) and fill the divot 36. The subsequently formed transistor is then no longer the transistor that was designed because of the remaining polysilicon 44 in the divot 36. The polysilicon strings 44 are often left after gate etch, for example, in STI divots 36 and this is a very common defect which can cause electrical shorts between gates. Again, this becomes more critical as the devices are reduced in size, as discussed supra because the polysilicon string 44 becomes a larger contributing factor to errors in the semiconductor device.
Referring now to
The process 700 begins at 702, wherein at 704 of
In an alternate embodiment at 710 acts 704, 706 and 708 are eliminated from the process, for example. At 712 of
The exemplary method 700 continues at 718, for example, wherein if an unacceptable polysilicon string is detected than corrective actions can be taken to repair the in-process device. The repair techniques are widely known in the art by those of ordinary skill. If the in-process device is deemed acceptable at 718 the processing continues at 720, for example.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
