Patent Application
20090261406
Embodiments in accordance with the present invention generally relate to semiconductor devices such as flash memory cells.
A traditional flash memory cell has a programmed state and an erased state. In the programmed state, a quantity or level of electrical charge is stored in a charge storage element. In the erased state, the charge is removed. The threshold voltage associated with the programmed state is higher than the threshold voltage associated with the erased state. A read voltage is applied to the memory cell—if a current is detected at the read voltage, the cell is read as erased; otherwise, the cell is read as programmed.
A typical memory cell cycles between the programmed state and the erased state many times during its lifetime. As the number of cycles increases, the memory cell in the erased state may not be sufficiently discharged, resulting in sub-threshold slope (STS) degradation. Consequently, the voltage difference between the programmed and erased states may decrease, making it more difficult to distinguish between the two states. As a result, a read error may occur—for example, if the memory cell is not sufficiently discharged, then it may be read as being in the programmed state when in fact it is in the erased state.
Accordingly, a solution for STS degradation in memory cells would be advantageous. Embodiments in accordance with the present invention provide this and other advantages.
According to an embodiment of the present invention, a flash memory cell includes a charge storage element. The charge storage element includes at least a first layer and a second layer, which have different compositions of silicon nitride, respectively. One of the layers includes silicon-rich silicon nitride and the other layer includes silicon nitride. The introduction of silicon-rich silicon nitride in the charge storage element ameliorates the effects of STS degradation, reducing the number of read errors associated with STS degradation and thus improving the performance of memory cells.
These and other objects of the various embodiments of the present invention and their advantages will be recognized by those of ordinary skill in the art after reading the following detailed description of the embodiments that are illustrated in the various drawing figures.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:
The drawings referred to in this description should be understood as not being drawn to scale except if specifically noted.
Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.
Some portions of the detailed descriptions that follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations for fabricating semiconductor devices. These descriptions and representations are the means used by those skilled in the art of semiconductor device fabrication to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, or the like, is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present application, discussions utilizing terms such as “forming,” “performing,” “producing,” “depositing,” “filling,” “implanting” or the like, refer to actions and processes of semiconductor device fabrication.
In
In the example of
A charge storage element 108 is disposed between the gate element 114 and the substrate 102. In the embodiment of
Generally speaking, the ratio of silicon-to-nitrogen in the silicon-rich silicon nitride layer 110 is greater than the ratio of silicon-to-nitrogen in the silicon nitride layer 112. More specifically, silicon-rich silicon nitride is a type of silicon nitride that has a greater number of silicon atoms than the number of silicon atoms in stoichiometric silicon nitride. Stoichiometric silicon nitride has the chemical formula SixNy where x=3 and y=4. While silicon-rich silicon nitride also has the chemical formula SixNy, it has a composition where the ratio of x-to-y is greater than three-fourths. Silicon-rich silicon nitride has more desirable conductive properties relative to stoichiometric silicon nitride. Silicon-rich silicon nitride tends to have shallower trap energy levels and higher trap density, both of which allow electrons to move easily to enable more effective Fowler-Nordheim programming and erasing.
When the memory cell 100 is programmed, a relatively uniform charge is trapped across the whole channel (across the width of the charge storage element 108, where width is measured left-to-right considering the orientation of the memory cell in
The charge storage 108 element may be separated from the substrate 102 by an oxide layer 106 (which may be referred to as a bottom oxide or tunnel oxide layer). The charge storage element 108 may be separated from the gate element 114 by a top oxide layer or a high-k (high dielectric constant) material layer 107. The high-k material has a dielectric constant greater than that of silicon dioxide.
A spacer 120 is formed on each side of the memory cell 110. The spacer 120 may be formed using a nitride material or an oxide material. The spacer 120 may be separated from the elements of the memory cell 110 by one or more oxide layers 104 (e.g., the oxide layer 104 may include an implant oxide layer and a spacer liner oxide layer).
In general, a memory array includes a number of word lines and a number of bit lines that are disposed orthogonal to the word lines. The charge storage element 108 is adjacent to each of the word lines. In one embodiment, a memory cell includes a portion of a word line and its associated charge storage element as well as a portion of two neighboring bit lines. In one such embodiment, the source/drain regions, which correspond to the two neighboring bit lines, are interchangeable with each other—that is, when one region operates as a source, the other operates as a drain, and vice versa. Charge storage elements can be continuous under the layer 118 (e.g., the polysilicon layer) or they can be isolated for each memory cell.
In addition to the flash memory cell embodiments described above, features of the invention can be incorporated into flash memory cells such as, but not limited to, SONOS (semiconductor-oxide-nitride-oxide-semiconductor) architectures and TANOS (tantalum-alumina-nitride-oxide-semiconductor) architectures. That is, for example, the nitride layer referred to in the SONOS and TANOS architectures can be modified to include a silicon-rich silicon nitride layer along with one or more silicon nitride layers in the manner described above.
Various techniques known in the art are used to fabricate a semiconductor device such as a memory cell. In general, these techniques involve repeating, with variations, a number of characteristic steps or processes. One of these characteristic steps or processes involves applying a layer of material to an underlying substrate or to a preceding layer, and then selectively removing the material using, for example, an etch process. Another of the characteristic steps or processes involves selectively adding a dopant material to the substrate or to one or more of the subsequent layers, in order to achieve desirable electrical performance. Using these characteristic processes, a semiconductor, generally comprising different types of material, can be accurately formed. These characteristic processes are known in the art, and so are not elaborated upon herein.
In block 330, a layer of silicon nitride (e.g., the layer 112 or the layer 214) is deposited. Because the amount of silicon may be reduced during a subsequent oxidation step, the amount of silicon deposited in the first, second and third layers may be greater than the amount of silicon desired in the final product.
In block 340, a gate element is formed. In one embodiment, an oxide layer (e.g., the layer 107) is formed.
As part of the method above, spacers and other oxide layers (e.g., the implant oxide layer and the spacer liner oxide layer) can be formed.
In summary, a charge storage element in a memory cell includes a silicon-rich silicon nitride layer in addition to one or more layers of silicon nitride. The introduction of a silicon-rich silicon nitride layer in the charge storage element ameliorates the effects of STS degradation, reducing the number of read errors and improving performance.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.
