Korean Patent Application No. 10-2018-0099186, filed on Aug. 24, 2018, in the Korean Intellectual Property Office, and entitled: “Variable Resistance Memory Device,” is incorporated by reference herein in its entirety.
Embodiments relate to a variable resistance memory device and, more particularly, to a variable resistance memory device with improved reliability.
Semiconductor devices have been highly integrated to provide excellent performance and low manufacture costs. The integration density of semiconductor devices directly affects the costs of the semiconductor devices, thereby resulting in a demand of highly integrated semiconductor devices. The integration density of typical two-dimensional (2D) or planar semiconductor devices may be mainly determined by an area which a unit memory cell occupies. Therefore, the integration density of the typical 2D or planar semiconductor devices may be greatly affected by a technique of forming fine patterns. However, since extremely high-priced apparatuses are needed to form fine patterns, the integration density of 2D semiconductor devices continues to increase but is still limited. Three-dimensional (3D) semiconductor devices including three-dimensionally arranged memory cells have been developed to overcome these limitations. In addition, next-generation semiconductor memory devices, e.g., magnetic random access memory (MRAM) devices and phase-change random access memory (PRAM) devices, have been developed to provide high-performance and low power consuming semiconductor memory devices.
In an aspect, a variable resistance memory device may include an interlayer insulating structure having a hole on a substrate, a bottom electrode disposed in a lower portion of the hole, and a pattern disposed in an upper portion of the hole. The pattern may include at least one of a phase change pattern or an intermediate electrode. A sidewall of the pattern may form an angle with a top surface of the substrate, and the angle may decrease as a vertical distance from the substrate increases.
In an aspect, a variable resistance memory device may include an interlayer insulating structure having a hole on a substrate, a bottom electrode disposed in a lower portion of the hole, and a pattern disposed in an upper portion of the hole. The pattern may include at least one of a phase change pattern or an intermediate electrode, and a sidewall of the pattern may be concave.
In an aspect, a variable resistance memory device may include an interlayer insulating structure having a hole on a substrate, a bottom electrode disposed in a lower portion of the hole, and a phase change pattern disposed in an upper portion of the hole. A first gradient of a sidewall of the lower portion of the hole may be greater than a second gradient of a sidewall of the upper portion of the hole.
Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
Referring to
Interlayer insulating structures 105 may be disposed on the substrate 100. The interlayer insulating structures 105 may be disposed on the first conductive lines CL1. Each of the interlayer insulating structures 105 may have vertical holes VRP penetrating the interlayer insulating structure 105. The vertical holes VRP may be spaced apart from each other and may be arranged in the first direction X and the second direction Y. The vertical holes VRP may include first vertical holes VRP1 and second vertical holes VRP2, which are arranged in the first direction X on each of the first conductive lines CL1. The first vertical holes VRP1 and the second vertical holes VRP2 may be alternately arranged in the first direction X. The vertical holes VRP may expose top surfaces of the first conductive lines CL1.
Each of the interlayer insulating structures 105 may include horizontal holes PRP. The horizontal holes PRP may expose the top surfaces of the first conductive lines CL1. Each of the horizontal holes PRP may be disposed between a pair of the first vertical hole VRP1 and the second vertical hole VRP2 adjacent to each other in the first direction X and may connect the pair of the first and second vertical holes VRP1 and VRP2. For example, as illustrated in
Each of the interlayer insulating structures 105 may include first interlayer insulating patterns 105a and second interlayer insulating patterns 105b. The first interlayer insulating patterns 105a and the second interlayer insulating patterns 105b may be alternately arranged in the first direction X on the top surface of each of the first conductive lines CL1.
For example, each of the first interlayer insulating patterns 105a may be disposed on the first conductive line CL1 between a pair of the first and second vertical holes VRP1 and VRP2 and another pair of the first and second vertical holes VRP1 and VRP2. Here, the pair of first and second vertical holes VRP1 and VRP2 may be adjacent to each other in the first direction X, and the other pair of first and second vertical holes VRP1 and VRP2 may be adjacent to each other in the first direction X. For example, as illustrated in
For example, each of the second interlayer insulating patterns 105b may be disposed on the first conductive line CL1 between the first vertical hole VRP1 and the second vertical hole VRP2. For example. as illustrated in
A first sidewall S1 of each of the vertical holes VRP may be formed or defined by the first interlayer insulating pattern 105a. A second sidewall S2 of each of the vertical holes VRP, which is opposite to the first sidewall S1, may be formed or defined by the second interlayer insulating pattern 105b. Referring to
In some embodiments, referring to
The bottom electrodes BE may be disposed in the vertical holes VRP. The bottom electrodes BE may be spaced apart from each other and may be arranged in the first direction X and the second direction Y when viewed in a plan view. Each of the bottom electrodes BE may be disposed on the first sidewall S1 of the lower portion LP of each of the vertical holes VRP, e.g., each bottom electrode BE may be disposed on the first sidewall S1 in each of the first and second vertical holes VRP1 and VRP2. The bottom electrode BE may be in, e.g., direct, contact with the first sidewall S1 of the lower portion LP of the vertical hole VRP and the first conductive line CL1. For example, the bottom electrodes BE may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.
A horizontal connection pattern 110 may be disposed in each of the horizontal holes PRP. For example, the horizontal connection pattern 110 may be connected to the bottom electrodes BE disposed in the pair of the first and second vertical holes VRP1 and VRP2. In other words, the horizontal connection pattern 110 may connect the bottom electrode BE disposed in the first vertical hole VRP1 to the bottom electrode BE disposed in the second vertical hole VRP2. The horizontal connection pattern 110 may be in contact with the top surface of the first conductive line CL1. The horizontal connection pattern 110 may include the same material as the bottom electrode BE. For example, the horizontal connection pattern 110 may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.
The spacers SP may be disposed in the vertical holes VRP. The spacers SP may be spaced apart from each other and may be arranged in the first direction X and the second direction Y when viewed in a plan view. Each of the spacers SP may be disposed on the second sidewall S2 of the lower portion LP of each of the vertical holes VRP. The spacer SP may be disposed on one sidewall of the bottom electrode BE, e.g., each spacer SP may be between the second sidewall S2 and a corresponding bottom electrode BE in each of the first and second vertical holes VRP1 and VRP2. The spacer SP may be in contact with the bottom electrode BE and the second sidewall S2 of the lower portion LP of the vertical hole VRP. For example, the spacer SP may include silicon oxide or poly-silicon.
A horizontal spacer 120 may be disposed on a top surface of the horizontal connection pattern 110 in each of the horizontal holes PRP. For example, the horizontal spacer 120 may be connected to the spacers SP disposed in the pair of first and second vertical holes VRP1 and VRP2. In other words, the horizontal spacer 120 may connect the spacer SP disposed in the first vertical hole VRP1 to the spacer SP disposed in the second vertical hole VRP2. The horizontal spacer 120 may be in contact with the horizontal connection pattern 110 and the second interlayer insulating pattern 105b. The horizontal spacer 120 may include the same material as the spacer SP. For example, the horizontal spacer 120 may include silicon oxide or poly-silicon. For example, as illustrated in
The phase change pattern 130 may be disposed on the topmost surfaces of the bottom electrode BE and the spacer SP in each of the vertical holes VRP. The phase change patterns 130 may be spaced apart from each other and may be arranged in the first direction X and the second direction Y. Each of the phase change patterns 130 may be disposed in the lower portion LP and the upper portion UP of each of the vertical holes VRP. Each of the phase change patterns 130 may be in contact with the first and second sidewalls S1 and S2 of the lower and upper portions LP and UP of each of the vertical holes VRP. The phase change patterns 130 may include at least one material having properties capable of storing data or information. In some embodiments, the phase change patterns 130 may include a material of which a phase is reversibly changeable between a crystalline state and an amorphous state by temperature. For example, the phase change patterns 130 may be formed of a compound that includes at least one of Te or Se (i.e., chalcogenide elements) and at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, or C. For example, the phase change patterns 130 may include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, or InSbTe.
In other embodiments, the phase change patterns 130 may include at least one of a perovskite compound or a conductive metal oxide. For example, the phase change patterns 130 may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr,Ca)MnO3 (PCMO), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, or barium-strontium-zirconium oxide. When the phase change patterns 130 include a transition metal oxide, a dielectric constant of the phase change patterns 130 may be greater than a dielectric constant of silicon oxide. In still other embodiments, the phase change patterns 130 may have a double-layer structure of a conductive metal oxide layer and a tunnel insulating layer or may have a triple-layer structure of a first conductive metal oxide layer, a tunnel insulating layer and a second conductive metal oxide layer. The tunnel insulating layer may include aluminum oxide, hafnium oxide, or silicon oxide.
Referring to
The intermediate electrode ME may be disposed on the top surface 132 of the phase change pattern 130 in each of the vertical holes VRP. The intermediate electrode ME may be disposed in the upper portion UP of the vertical hole VRP. The intermediate electrode ME may be in contact with the first and second sidewalls S1 and S2 of the upper portion UP of the vertical hole VRP. A top surface of the intermediate electrode ME may be substantially coplanar with the top surface of the interlayer insulating structure 105. For example, the intermediate electrode ME may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.
Referring to
Referring back to
As illustrated in
Top electrodes UE may be disposed on top surfaces of the switching patterns 150. The top electrodes UE may be connected to the switching patterns 150. For example, the top electrodes UE may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO. A fourth interlayer insulating layer 160 may be disposed on the top surfaces of the interlayer insulating structures 105 and the top surfaces of the third interlayer insulating patterns 140. The fourth interlayer insulating layer 160 may cover sidewalls of the switching patterns 150 and sidewalls of the top electrodes UE. A top surface of the fourth interlayer insulating layer 160 may be substantially coplanar with top surfaces of the top electrodes UE. For example, the fourth interlayer insulating layer 160 may include a silicon nitride layer.
Second conductive lines CL2 may be disposed on the top surfaces of the top electrodes UE. Each of the second conductive lines CL2 may extend in the second direction Y along the top electrodes UE arranged in the second direction Y. The second conductive lines CL2 may be spaced apart from each other and may be arranged in the first direction X. Each of the second conductive lines CL2 may be electrically connected to the phase change patterns 130 arranged in the second direction Y. In some embodiments, the second conductive lines CL2 may be bit lines. For example, the second conductive lines CL2 may include at least one of a metal material (e.g., copper or aluminum) or a conductive metal nitride (e.g., TiN or WN).
Referring to
Referring to
The phase change pattern 130 may include the first portion P1 disposed between the bottom electrode BE and the intermediate electrode ME and between the spacer SP and the intermediate electrode ME, and the second portion P2 disposed between the first portion P1 and the intermediate electrode ME. The first portion P1 may be disposed in the lower portion LP of the vertical hole VRP, and the second portion P2 may be disposed in the upper portion UP of the vertical hole VRP. In some embodiments, the second portion P2 of the phase change pattern 130 may correspond to the pattern 1 illustrated in
The intermediate electrode ME may be disposed on the top surface 132 of the phase change pattern 130. A top surface of the intermediate electrode ME may be located at a higher level than the top surface of the interlayer insulating structure 105. A sidewall SW3 of the intermediate electrode ME may be covered by the fourth interlayer insulating layer 160. The intermediate electrode ME may be spaced apart from the first and second sidewalls S1 and S2 of the upper portion UP of the vertical hole VRP. The sidewall SW3 of the intermediate electrode ME may form a substantially right angle with the top surface of the substrate 100 (θ3=90°). The first width W1′ of the bottom surface of the intermediate electrode ME may be substantially equal to the second width W2′ of the top surface of the intermediate electrode ME (W1′=W2′). The second width W2 of the top surface 132 of the phase change pattern 130 may be substantially equal to the first width W1′ and the second width W2′ of the intermediate electrode ME (W2=W1′=W2′). The sum of the third width W3 of the bottom electrode BE and the fourth width W4 of the spacer SP may be less than each of the first width W1′ and the second width W2′ of the intermediate electrode ME (W3+W4<W1′=W2′).
Referring to
A first interlayer insulating layer 201 may be formed on the substrate 100 to cover the first conductive lines CL1, and first trenches T1 may be formed in the first interlayer insulating layer 201. The first trenches T1 may be formed by patterning the first interlayer insulating layer 201 and may expose portions of top surfaces of the first conductive lines CL1. The first trenches T1 may extend in the second direction Y to intersect the first conductive lines CL1 and may be spaced apart from each other in the first direction X. A width of each of the first trenches T1 may become progressively greater from its bottom end toward its top end. In other words, sidewalls of the first trenches T1 may be inclined with respect to the top surface of the substrate 100. Alternatively, the sidewalls of the first trenches T1 may be substantially perpendicular to the top surface of the substrate 100. For example, the first interlayer insulating layer 201 may include a silicon nitride layer.
Bottom electrode layers BEL may be formed in the first trenches T1, respectively. In some embodiments, a metal layer may be formed to conformally cover bottom surfaces and sidewalls of the first trenches T1 and a top surface of the first interlayer insulating layer 201, and a planarization process may be performed on the metal layer until the top surface of the first interlayer insulating layer 201 is exposed, thereby forming the bottom electrode layers BEL. The bottom electrode layers BEL may conformally cover the bottom surfaces and the sidewalls of the first trenches T1. The bottom electrode layers BEL may be in contact with the first conductive lines CL1. For example, the bottom electrode layers BEL may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.
Spacer layers SPL may be formed on the bottom electrode layers BEL, respectively. In some embodiments, a silicon layer (or a silicon oxide layer) may be formed to conformally cover the bottom electrode layers BEL formed in the first trenches TI and the first interlayer insulating layer 201, and a planarization process may be performed on the silicon layer (or the silicon oxide layer) until the top surface of the first interlayer insulating layer 201 is exposed, thereby forming the spacer layers SPL. The spacer layers SPL may conformally cover the bottom electrode layers BEL, respectively. For example, the spacer layers SPL may include silicon oxide or poly-silicon.
Second interlayer insulating layers 203 may be formed in the first trenches T1, respectively. In some embodiments, an insulating layer filling the first trenches T1 and covering the spacer layers SPL and the first interlayer insulating layer 201 may be formed, and a planarization process may be performed on the insulating layer until the top surface of the first interlayer insulating layer 201 is exposed, thereby forming the second interlayer insulating layers 203. For example, the second interlayer insulating layers 203 may include silicon nitride. In certain embodiments, the metal layer, the silicon layer (or the silicon oxide layer) and the insulating layer may be sequentially formed on the substrate 100 having the first trenches T1, and a planarization process may be performed on the insulating layer, the silicon layer (or the silicon oxide layer) and the metal layer until the first interlayer insulating layer 201 is exposed, thereby forming the bottom electrode layers BEL, the spacer layers SPL, and the second interlayer insulating layers 203 in the first trenches T1.
Referring to
The first interlayer insulating patterns 105a may be formed by patterning the first interlayer insulating layer 201. The first interlayer insulating patterns 105a may overlap with the first conductive lines CL1, and each of the first interlayer insulating patterns 105a may be disposed between the first trenches T1 adjacent to each other in the first direction X. The first interlayer insulating patterns 105a may be in contact with top surfaces of the first conductive lines CL1. The second interlayer insulating patterns 105b may be formed by patterning the second interlayer insulating layers 203. The second interlayer insulating patterns 105b may be formed in the first trenches T1. In some embodiments, the first interlayer insulating patterns 105a and the second interlayer insulating patterns 105b may be alternately arranged in the first direction X on each of the first conductive lines CL1.
The pair of bottom electrodes BE and the horizontal connection pattern 110 may be formed by the patterning of the bottom electrode layer BEL. The pair of bottom electrodes BE and the horizontal connection pattern 110 may be formed in each of the first trenches T1. One of the pair of bottom electrodes BE may be disposed on one sidewall of the first trench T1, which is parallel to the second direction Y. The other of the pair of bottom electrodes BE may be disposed on another sidewall of the first trench T1, which is opposite to the one sidewall of the first trench T1. The horizontal connection pattern 110 may be formed on the bottom surface of the first trench T1. The horizontal connection pattern 110 may connect the pair of bottom electrodes BE formed in each of the first trenches T1. For example, as illustrated in
The pair of spacers SP and the horizontal spacer 120 may be formed by the patterning of the spacer layer SPL. The pair of spacers SP and the horizontal spacer 120 may be formed in each of the first trenches T1. One of the pair of spacers SP may be disposed on a sidewall of one of the pair of bottom electrodes BE, and the other of the pair of spacers SP may be disposed on a sidewall of the other of the pair of bottom electrodes BE. The horizontal spacer 120 may be formed on a top surface of the horizontal connection pattern 110. The horizontal spacer 120 may connect the pair of spacers SP formed in each of the first trenches T1. For example, as illustrated in
The third interlayer insulating patterns 140 may be formed in the second trenches T2. In some embodiments, an insulating layer may be formed to fill the second trenches T2 and to cover top surfaces of the spacers SP, top surfaces of the bottom electrodes BE, top surfaces of the first interlayer insulating patterns 105a, and top surfaces of the second interlayer insulating patterns 105b. Then, a planarization process may be performed on the insulating layer to locally form the third interlayer insulating patterns 140 in the second trenches T2, respectively. The third interlayer insulating patterns 140 may extend in the first direction X and may be spaced apart from each other in the second direction Y. Top surfaces of the third interlayer insulating patterns 140 may be substantially coplanar with the top surfaces of the first and second interlayer insulating patterns 105a and 105b. For example, the third interlayer insulating patterns 140 may include silicon nitride.
Referring to
Referring to
The etching process may be performed by, e.g., a dry cleaning process, a dry etching process, or a wet etching process. For example, the dry cleaning process may be a chemical oxide removal (COR) process or a pulsed dry cleaning (PDC) process. For example, the dry etching process may be an ion beam etch (IBE) process, a CF4 treatment process, or a chemical oxide removal (COR) process. For example, the wet etching process may use an etching solution, e.g., O3HF, HF, or SC1. After expanding the widths of the upper portions of the inner spaces IS, the etch by-product BYP may be removed. The etch by-product BYP may be evaporated by a thermal treatment process. The thermal treatment process may be performed at about 70 degrees Celsius or more. The top surfaces of the first to third interlayer insulating patterns 105a, 105b and 140, and the sidewalls of the inner spaces IS may be exposed by the removal of the etch by-product BYP.
Referring to
In other embodiments, the phase change patterns 130 may include at least one of a perovskite compound or a conductive metal oxide. For example, the phase change patterns 130 may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, (Pr,Ca)MnO3 (PCMO), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide. barium-zirconium oxide, or barium-strontium-zirconium oxide. When the phase change patterns 130 include a transition metal oxide, a dielectric constant of the phase change patterns 130 may be greater than a dielectric constant of silicon oxide. In still other embodiments, the phase change patterns 130 may have a double-layer structure of a conductive metal oxide layer and a tunnel insulating layer or may have a triple-layer structure of a first conductive metal oxide layer, a tunnel insulating layer and a second conductive metal oxide layer. The tunnel insulating layer may include aluminum oxide, hafnium oxide, or silicon oxide.
According to the embodiments, the etching process may be performed to expand or enlarge the widths of the upper portions of the inner spaces IS, and thus the phase change patterns 130 may fill the inner spaces IS without a void. As a result, reliability of the variable resistance memory device may be improved.
Referring again to
In certain embodiments, a conductive layer may be formed to cover the top surfaces of the phase change patterns 130 and the top surfaces of the first to third interlayer insulating patterns 105a, 105b and 140, and the conductive layer may be patterned to form the intermediate electrodes ME. In this case, the intermediate electrodes ME may not be formed in the inner spaces IS, as illustrated in
The switching pattern 150 and the top electrode UE may be sequentially formed on the top surface of each of the intermediate electrodes ME. In some embodiments, a switching layer and a metal layer may be sequentially formed on the top surfaces of the first to third interlayer insulating patterns 105a, 105b and 140, and then, the metal layer and the switching layer may be patterned to form the switching patterns 150 and the top electrodes UE. Each of the switching patterns 150 may be a diode or may be an element based on a threshold switching phenomenon having a nonlinear I-V curve (e.g., a S-shaped I-V curve).
For example, each of the switching patterns 150 may be an ovonic threshold switch (OTS) element having a bi-directional characteristic. In some embodiments, the switching pattern 150 may be the diode. In this case, the switching pattern 150 may include a first junction pattern and a second junction pattern. The first junction pattern may have a first conductivity type, and the second junction pattern may have a second conductivity type different from the first conductivity type. For example, the first conductivity type may be an N type, and the second conductivity type may be a P type. For example, the second junction pattern may include dopants of the second conductivity type. The first junction pattern may include dopants of the first conductivity type and dopants of the second conductivity type. In this case, a concentration of the first conductivity type dopants may be higher than a concentration of the second conductivity type dopants, in the first junction pattern. In some embodiments, the switching pattern 150 may be a silicon diode or oxide diode which has a rectifying property. For example, the switching pattern 150 may be a silicon diode of P-type silicon and N-type silicon or may be an oxide diode of P-type NiOx and N-type TiOx or an oxide diode of P-type CuOx and N-type TiOx. For example, the top electrodes UE may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.
The fourth interlayer insulating layer 160 may be formed on the first to third interlayer insulating patterns 105a, 105b, and 140. The fourth interlayer insulating layer 160 may cover the top surfaces of the first to third interlayer insulating patterns 105a, 105b and 140, sidewalls of the switching patterns 150, and sidewalls of the top electrodes UE. For example, the fourth interlayer insulating layer 160 may include a silicon nitride layer. Second conductive lines CL2 may be formed on top surfaces of the top electrodes UE. Each of the second conductive lines CL2 may extend in the second direction Y along the top electrodes UE arranged in the second direction Y. Each of the second conductive lines CL2 may be connected to the top electrodes UE arranged in the second direction Y. For example, the second conductive lines CL2 may include at least one of a metal material (e.g., copper or aluminum) or a conductive metal nitride (e.g., TiN or WN).
By way of summation and review, embodiments provide a variable resistance memory device with improved reliability. That is, according to the embodiments, an etching process may be performed to expand or enlarge the widths of the upper portions of the inner spaces surrounded by the interlayer insulating patterns, e.g., so the inner spaces with high aspect ratios may have wide tops and curved corners at the tops. As such, the filling ability of the deposited material may be improved within the inner spaces, so the phase change patterns may fill the inner spaces without a void. As a result, the reliability of the variable resistance memory device may be improved.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Number | Date | Country | Kind |
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10-2018-0099186 | Aug 2018 | KR | national |