Versatile semiconductor test structure array

Abstract

This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUTs) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a test structure array in accordance with one embodiment of the present invention.

FIG. 2 schematically illustrates a unit cell of the test structure array.

FIGS. 3A˜3C schematically illustrates connections of sample devices under test (DUT).

FIGS. 4A˜4C schematically illustrate three examples of a controlled transmission gate (CTG) used in unit cells of the test structure array.

FIG. 5 schematically illustrates a resistor under test as an example for optimizing transistor sizes in transmission gates.

Claims

1. A semiconductor test structure array comprising: a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; andan access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,wherein the access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.

2. The semiconductor test structure array of claim 1, wherein at least one CTG further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate.

3. The semiconductor test structure array of claim 2, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.

4. The semiconductor test structure array of claim 1, wherein at least one CTG further comprises one or more NMOS transistors connected as a transmission gate.

5. The semiconductor test structure array of claim 4, wherein the NMOS transistors have predetermined channel width-over-length ratios to ensure the NMOS transistors operate in linear regions for a given device under test.

6. The semiconductor test structure array of claim 1, wherein at least one CTG further comprises one or more PMOS transistors connected as a transmission gate.

7. The semiconductor test structure array of claim 6, wherein the PMOS transistors have predetermined channel width-over-length ratios to ensure the PMOS transistors operate in linear regions for a given device under test.

8. The semiconductor test structure array of claim 1 further comprising a row decoder and a column decoder for addressing the unit cells.

9. The semiconductor test structure array of claim 1, wherein the number of CTGs in an access-control circuitry is at least four.

10. The semiconductor test structure array of claim 1, wherein each access-control circuitry further comprises one or more address decoders to simultaneously control the CTGs contained therein.

11. The semiconductor test structure array of claim 1, wherein the corresponding CTGs in a plurality of unit cells of a row are coupled to a row data-line.

12. The semiconductor test structure array of claim 1, wherein the corresponding CTGs in a plurality of unit cells of a column are coupled to a column data-line.

13. A semiconductor test structure array comprising: a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; andan access-control circuitry within the each unit cell for controlling accesses to the one or more DUTs,wherein the access-control circuitries are isomorphic and the each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), andwherein at least one of the CTGs further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.

14. The semiconductor test structure array of claim 13 further comprising a row decoder and a column decoder for addressing the unit cells.

15. The semiconductor test structure array of claim 13, wherein the number of CTGs in an access-control circuitry is at least four.

16. The semiconductor test structure array of claim 13, wherein the each access-control circuitry further comprises one or more address decoders to simultaneously control the CTGs contained therein.

17. The semiconductor test structure array of claim 13, wherein the corresponding CTGs in a plurality of unit cells of a row are coupled to a row data-line.

18. The semiconductor test structure array of claim 13, wherein the corresponding CTGs in a plurality of unit cells of a column are coupled to a column data-line.

19. A semiconductor test structure array comprising: a row decoder;a column decoder;a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array; andan access-control circuitry within the each unit cell for controlling accesses to the one or more DUTs,wherein the access-control circuitries are isomorphic and the each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), andwherein the CTG further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.

20. The semiconductor test structure array of claim 19, wherein each access-control circuitry further comprises one or more address decoders to simultaneously control the CTGs contained therein.