Vertical heterojunction bipolar transistor

Abstract

A heterojunction bipolar transistor (20, 60) is provided with a silicon (Si) base region (34, 74) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36, 72) proximate the base region (34, 74) and a distal gallium phosphide (GaP) emitter layer (40, 66). The GaAs emitter layer (36, 72) is sufficiently thin, preferably less than 200 Å, so as to be coherently strained. In one embodiment, the GaP emitter layer includes a doped region (70) that serves as the emitter and an undoped region (68) on which the intrinsic portion of the transistor (60) is formed.

Description

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to heterojunction bipolar transistors (HBTs).

BACKGROUND OF THE INVENTION

[0003] Heterojunction bipolar transistors (HBTs) theoretically provide advantages over conventional homojunction bipolar transistors by providing a heterojunction between a base and emitter of a transistor. A heterojunction is formed between two dissimilar semiconductor materials. Silicon (Si) exhibits a bandgap of around 1.12 eV, but a Si homojunction has no bandgap discontinuity at the junction. A bandgap discontinuity can occur at a junction by using dissimilar semiconductor materials on opposing sides of the junction. From the perspective of an NPN transistor, discontinuity in the valence band restricts hole flow from the base to the emitter, thus improving emitter injection efficiency and current gain. To the extent that injection efficiency and current gain improvements can be achieved, base region resistivity may be lowered (which lowers the base resistance) and emitter region resistivity may be raised (which lowers base-emitter junction capacitance) to create fast transistors without significantly compromising other device parameters. Such fast transistors would be useful for high-speed digital, microwave, and other integrated circuit and discrete transistor applications.

[0004] In practice, HBT performance often falls far short of the theoretical expectations. One conventional Si-based HBT reduces the bandgap of the base region by creating a base material having a narrower bandgap than Si. In particular, a small amount of germanium (Ge) is mixed with Si in the base (Si1−xGex), and the emitter is more purely Si. Unfortunately, the amount of bandgap difference (ΔEg) for as much as 20% Ge content in the base is only about 0.15 eV. This small ΔEg achieves only a small portion of the performance benefits that HBTs theoretically promise.

[0005] Slight improvements in HBT performance have been achieved by using materials other than Si for the emitter of an HBT. Three emitter materials which have been investigated for use in HBT transistors are silicon carbide (SiC), which has a bandgap of 2.93 eV, gallium arsenide (GaAs) which has a bandgap of 1.42 eV, and gallium phosphide (GaP), which has a bandgap of 2.24 eV. Unfortunately, such materials have lattice constants that differ from Si. For example, SiC has a 20% lattice mismatch, GaAs has a 4% lattice mismatch, and GaP has a 0.34% lattice mismatch. Likewise, such materials have thermal expansion coefficients that differ from Si. SiC has a thermal expansion coefficient of about 2.6×10−6(°C.)−1, while GaAs has a thermal expansion coefficient of around 6.7×10−6(°C.)−1, and GaP has a thermal expansion coefficient of around 5.91×10−6(°C.)−1. Because of these differences, only thin layers of these materials have been successfully grown on Si without the formation of significant defects. The maximum thickness for a low defect layer of SiC grown on Si is only a few angstroms (Å), and for GaAs grown on Si is less than 200 Å. At these thicknesses or less, strain, which is caused by lattice mismatch, is contained by lattice stretching rather than crystal defects. Thinner, low-defect thicknesses of these materials do not possess a sufficient thickness to protect the base-emitter junction from shorting due to diffusion of metal from the emitter contact region. Thicker, high-defect thicknesses of these materials exhibit degraded junction performance due to an excessive number of defects.

[0006] The most successful HBT improvements to date are believed to have been achieved by forming a GaP layer over Si at the base-emitter junction. GaP is desirable because it has a relative large bandgap (i.e., about 2.24 eV) and little lattice mismatch with silicon (i.e., about 0.34%). Nevertheless, such conventional HBTs that use a GaP layer over Si still achieve only a small portion of the performance benefits that HBTs theoretically promise. The reason for this poor performance appears to be that a Si-GaP junction suffers from an unusually large amount of interdiffusion, where the Ga and P readily diffuse into the Si, and vice-versa. The interdiffusion between Si and GaP results in a poor semiconductor junction, with the metallurgical junction being displaced from the electrical junction. Accordingly, the performance gains that are suggested by the wide bandgap difference between a Si base and a GaP emitter are not achieved in practice because the resulting diffuse junction negates those potential gains.

[0007] In the field of photoelectric semiconductors, it is desirable to form compound structures using a Si substrate and direct gap semiconductor materials. A Si substrate is desirable for mechanical stability and because a manufacturing infrastructure exists for reliably mass producing rugged Si wafers at relatively low cost. The Si substrate is typically an extrinsic part of the photoelectric semiconductor not used in forming intrinsic photoelectric semiconductor junctions.

[0008] Compound structures using a Si substrate and direct gap semiconductor materials suffer from problems similar to those discussed above for HBTs. Namely, lattice constant and thermal expansion coefficients for direct gap semiconductors differ from Si. Consequently, in attempting to produce low-defect compound semiconductors having direct gap semiconductors and a Si substrate, conventional photoelectric semiconductors often include very thick, highly doped buffer layers between the Si substrate and direct gap materials. Such buffer layers may include indirect gap materials, such as GaP and others, but these indirect gap materials are unsuitable for intrinsic photoelectric semiconductors.

[0009] Such buffer layers tend to incrementally shift lattice constants and thermal expansion coefficients so that the intrinsic direct gap photoelectric semiconductor materials may then be grown with fewer defects. Such applications often form relatively thick buffer layers which themselves may have numerous defects, at least closer to a Si interface, that are of little consequence to the intrinsic photoelectric semiconductor. Needless to say, such buffer layers are not used in forming semiconductor junctions.

[0010] U.S. Pat. No. 5,912,481, which describes prior work of the inventors of the present invention, describes an HBT that goes a long way toward providing performance benefits that HBTs theoretically promise. However, further improvements in speed, radiation tolerance characteristics, and thermal dissipation would be desirable.

[0011] Speed and radiation tolerance characteristics can both be enhanced by using an improved substrate in which, or on which, an intrinsic transistor is formed. Conventional techniques apply a silicon on insulator (SOI) technology. Typically, an intrinsic transistor is formed over an SiO2 layer rather than over a semiconductor, such as Si. When hit by radiation, the SiO2 layer does not produce the electron disturbances that are characteristic of a semiconductor, leading to radiation tolerance improvements. In addition, the insulative SiO2 layer lowers capacitance, which leads to improvements in speed. However, SiO2 is not a particularly good thermal conductor. Consequently, less heat is conducted away from the intrinsic transistor, fewer transistors can be placed near one another on an integrated circuit, and higher power devices are not practical.

[0012] Moreover, one conventional SOI technique forms a crystalline layer (e.g., Si) used in the formation of intrinsic transistors over the SiO2 layer. Since Sio2 is a porous material, not a crystalline material, the overlying crystalline layer often exhibits defects that cannot be cured by annealing. Accordingly, poor yields result. Another conventional SOI technique forms a single Si crystal, then implants oxygen (O2) under high energy deep into the Si crystal and anneals to form a deep SiO2 layer. Unfortunately, getting complete and uniform SiO2 formation within an existing Si layer is extremely difficult. Consequently, this SOI technique is characterized by incomplete oxidation, which leads to a poor quality SiO2 layer and only marginal speed and radiation tolerance improvements.

SUMMARY OF THE INVENTION

[0013] Accordingly, it is an advantage of the present invention that an improved heterojunction bipolar transistor (HBT) having a wide bandgap with low interdiffusion base-emitter junction and method therefor are provided.

[0014] Another advantage is that an HBT having a multilayer emitter is provided.

[0015] Another advantage is that an HBT is provided which has a wide bandgap emitter along with a base-emitter junction that is substantially free of interdiffusion.

[0016] Another advantage is that an HBT is provided with a Si base region that forms a junction with a multilayer emitter having a thin GaAs layer proximate the base region and a distal GaP layer.

[0017] Another advantage is that an HBT is provided that exhibits performance that more closely meets theoretical expectations than conventional HBTs.

[0018] Another advantage is that an HBT is provided which uses a Si substrate and a substantially insulative crystalline layer grown thereon.

[0019] Another advantage is that an intrinsic HBT is formed in and on a substantially insulative layer that is also a good thermal conductor.

[0020] The above and other advantages of the present invention are carried out in one form by a vertical heterojunction bipolar transistor which includes a gallium phosphide layer (GaP) configured to exhibit a first conductivity type. The GaP layer forms a first portion of a multilayer emitter. A gallium arsenide (GaAs) layer is formed in contact with the GaP layer. The GaAs layer forms a second portion of the multilayer emitter. A silicon (Si) base region of a second conductivity type is formed in contact with the GaAs layer. In addition, a Si collector region of the first conductivity type is formed adjacent to the Si base region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] A more complete understanding of the present invention may be derived by referring to the detailed description and claims when considered in connection with the Figures, wherein like reference numbers refer to similar items throughout the Figures, and:

[0022] FIGS. 1-10 show sectional views of a first embodiment of an HBT at first through tenth processing stages, respectively;

[0023] FIG. 11 shows a schematic, zero biased, band diagram of a composite emitter HBT according to a preferred embodiment of the present invention; and

[0024] FIGS. 12-18 show sectional views of a second embodiment of an HBT at first through seventh processing stages, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] FIGS. 1-10 show sectional views of a heterojunction bipolar transistor (HBT) 20 configured in accordance with the present invention at first through tenth processing stages, respectively. The Figures illustrate an NPN implementation of the present invention, but those skilled in the art will realize that an equivalent PNP implementation is easily achieved by making routine substitutions well known to those skilled in the art.

[0026] FIG. 1 illustrates a first processing stage in which a buried region 22 is formed in a silicon (Si) substrate 24. Preferably, substrate 24 is lightly doped P-type conductivity, and buried region 22 is heavily doped through a standard ion implantation process to exhibit N-type conductivity for this NPN implementation.

[0027] FIG. 2 illustrates a second processing stage that follows the first processing stage depicted in FIG. 1. As illustrated in FIG. 2, a collector layer 26 is epitaxially grown on substrate 24. Buried region 22 is now diffused into both collector layer 26 and substrate 24. Collector layer 26 is a lightly doped N-type conductivity. Phosphorous, antimony, or arsenic N-type dopants are used through conventional techniques, such as ion implantation or diffusion, to achieve the desired conductivity type. Buried region 22 allows collector layer 26 to exhibit a low resistance while controlling the breakdown voltage of HBT 20. As understood by those skilled in the art, the thickness of collector layer 26 is selected to achieve application-specific goals. For example, collector layer 26 is desirably thinner to increase the speed of HBT 20 and thicker to increase the breakdown voltage of HBT 20.

[0028] FIG. 3 illustrates a third processing stage that follows the second processing stage depicted in FIG. 2. FIG. 3 shows several independent diffusion areas formed in collector layer 26. A highly doped P-type conductivity isolation diffusion area 28 is made to surround a collector region 30, which provides proper isolation for the final HBT 20. Collector region 30 will eventually serve as the collector of HBT 20. Diffusion area 28 desirably refrains from overlying any portion of buried region 22.

[0029] A highly doped N-type conductivity contact-enabling diffusion area 32 is made at a location within collector region 30 where a metallization layer will eventually make an electrical collector contact. This location desirably overlies a portion of buried layer 22.

[0030] A base region 34 is another diffusion area that is also formed within collector region 30. Base region 34 will eventually serve as the base of HBT 20. Base region 34 is doped to exhibit P-type conductivity for this NPN implementation. Desirably, base region 34 is heavily doped so that the base of HBT 20 will exhibit an unusually low resistance. Diffusion areas 28, 32, and 34 are formed using conventional ion implantation or other techniques. Isolation and contact-enabling diffusion areas 28 and 32 are desirably formed using a much higher acceleration voltage than base region 34 to drive diffusion areas 28 and 32 deeper into collector layer 26 than base region 34.

[0031] In an alternative embodiment, a small amount of germanium (Ge) is mixed with the Si of base region 34 to lower the bandgap of the base of HBT 20 when compared to the bandgap of a base formed using more pure Si. This mixing is desirably performed during the second stage depicted in FIG. 2. Small amounts of Ge (e.g., around 10%) with a P+ type doping can be mixed with the Si during only the later portion of epitaxial growth for collector layer 26 to form the base.

[0032] FIG. 4 illustrates a fourth processing stage that follows the third processing stage depicted in FIG. 3. FIG. 4 illustrates heat being applied to further drive diffusion areas 28, 32, and 34 deeper into collector layer 26. Isolation diffusion area 28 is desirably driven through collector layer 26 to substrate 24. Contact-enabling diffusion area 32 is desirably driven through collector region 30 to buried region 22. However, base region 34 is desirably driven only a shallow depth into collector layer 26. Desirably, base region 34 is around 1000 Å deep. However, the resulting base of HBT 20 will be shallower than this depth due to subsequent etching steps. This shallow depth of base region 34 leads to a low transit time, which increases the high current gain cut-off frequency (Ft) and high power gain cut-off frequency (Fmax) parameters for HBT 20.

[0033] During this fourth stage of processing, heat in excess of 800° C. may be applied to HBT 20 for extended periods of time. However, after this stage the temperature of HBT 20 is desirably maintained below 800° C. to prevent diffusion of non-silicon layers that will be grown over collector layer 26.

[0034] FIG. 5 illustrates a fifth processing stage that follows the fourth processing stage depicted in FIG. 4. FIG. 5 actually illustrates two epitaxial growth processes. The first epitaxial growth process grows a wide bandgap, non-silicon semiconductor, preferably gallium arsenide (GaAs), over and in contact with collector layer 26 to form a first emitter layer 36 of a multilayer emitter 38 (see FIG. 6). First emitter layer 36 may be of N-type conductivity for this NPN implementation or may not be intentionally doped, but is desirably configured so as not to exhibit P-type conductivity. A function of first emitter layer 36 is a diffusion barrier to provide a stable interface with the Si of base region 34.

[0035] The second epitaxial growth process grows a second non-silicon, wide bandgap semiconductor, preferably gallium phosphide (GaP), over and in contact with first emitter layer 36 to form a second emitter layer 40 of multilayer emitter 38. Desirably, second emitter layer 40 is degeneratively doped with a suitable N-type conductivity material for this NPN implementation, such as Si, to values in excess of 10×1020/cm3 to provide a very low emitter contact resistance where a metallization layer will eventually make an electrical emitter contact. Desirably, doping gradually increases as second emitter layer 40 builds away from first emitter layer 36 to reach the maximum value at the distal surface from first emitter layer 36. The function of second emitter layer 40 is to provide maximum valence band discontinuity with minimum lattice mismatch and minimal thermal expansion mismatch with respect to Si.

[0036] GaAs is a desirable material for use as an interface with Si because it can form an interface substantially free from interdiffusion, particularly when compared to the interdiffusion that results from forming a GaP layer on Si. In other words, an atomically abrupt interface forms between GaAs first emitter layer 36 and base region 34. Desirably, first emitter layer 36 is epitaxially grown using conventional techniques but at a relatively low temperature (e.g., 400-600° C.) to keep the Si—GaAs junction as free from interdiffusion as possible. Alternative cycles of even lower temperatures (e.g., 150-250° C.) may be applied during the growth process. This results in a substantially pure crystalline structure suitable for intrinsic semiconductor activity.

[0037] Moreover, first emitter layer 36 is limited in thickness so that first emitter layer 36 will be coherently strained between the Si of base region 34 and second emitter layer 40. Thickness is limited in a manner understood to those skilled in the art by controlling the time over which first emitter layer 36 is grown. A coherently strained layer is a layer so thin that lattice constant mismatches do not result in lattice mismatch crystal defects but are contained by lattice stretching. With first emitter layer 36 made from GaAs and second emitter layer 40 made from GaP, a thickness for first emitter layer 36 of less than 200 Å is preferred, with a thickness of less than 50 Å being particularly desirable.

[0038] The thickness of second emitter layer 40 is desirably much greater than the thickness of first emitter layer 36. Second emitter layer 40 is desirably at least 500 Å thick, and preferably around 2000-3000 Å thick. Less overall thickness is desired for multilayer emitter 38. Less thickness leads to a smaller emitter resistance and a faster HBT 20. However, the thickness of multilayer emitter 38, and primarily second emitter layer 40, is balanced with a need to prevent the emitter and base of HBT 20 from shorting. Shorting can occur when metallization, discussed below, diffuses through multilayer emitter 38 to reach base region 34. A sufficient thickness for second emitter layer 40 prevents metallization from diffusing therethrough.

[0039] Second emitter layer 40 is desirably grown epitaxially using standard techniques at temperatures that generally remain in the 400-600° C. range to preserve the substantially interdiffusion-free interface between first emitter layer 36 and base region 34. Although not shown, toward the upper regions of second emitter layer 40, distally removed from first emitter layer 36, temperature may be lowered so that this portion of second emitter layer 40 becomes polycrystalline. Among other benefits, this lessens the time HBT 20 spends at elevated temperatures to further lessen risks of interdiffusion at the base-emitter junction.

[0040] While first emitter layer 36 provides an abrupt interface with Si base region 34, second emitter layer 40 provides as great of a bandgap discontinuity as is practical. Thus, the bandgap characteristics of HBT 20 in the vicinity of the base-emitter junction are determined primarily by the bandgap differences between materials used for base region 34 and second emitter layer 40. However, the abruptness of the base-emitter junction (i.e., the congruence of the metallurgical and electrical junctions) is determined primarily by materials used for base region 34 and first emitter layer 36.

[0041] Due to the thin, coherently strained nature of first emitter layer 36, base region 34 exhibits few defects. Likewise, second emitter layer 40, although relatively thick, exhibits few defects in part because first emitter layer 36 is sufficiently thin to be coherently strained. Accordingly, not only does first emitter layer 36 provide a clean, abrupt semiconductor junction at base region 34, but first emitter layer 36 allows second emitter layer 40 to be epitaxially grown to a relatively thick width with few defects.

[0042] FIG. 6 illustrates a sixth processing stage that follows the fifth processing stage depicted in FIG. 5. FIG. 6 shows a patterning and etching process. Conventional photolithographic techniques can be used to pattern HBT 20, then etching is performed to remove portions of first and second emitter layers 36 and 40 that will not be used for multilayer emitter 38.

[0043] FIG. 7 illustrates a seventh processing stage that follows the sixth processing stage depicted in FIG. 6. FIG. 7 shows a passivation process. Conventional techniques are used to apply a passivation layer 42 over the entire surface of HBT 20 at this point. Silicon nitride, silicon dioxide, or other conventional passivation materials may be applied in a conventional manner, so long as temperatures generally remain below about 800° C.

[0044] FIG. 8 illustrates an eighth processing stage that follows the seventh processing stage depicted in FIG. 7. FIG. 8 shows another patterning and etching process. Conventional photolithographic techniques can be used to pattern HBT 20, then etching is performed to remove passivation layer 42 to form vias 44 in locations where a metallization layer will eventually make electrical contacts.

[0045] FIG. 9 illustrates a ninth processing stage that follows the eighth processing stage depicted in FIG. 8. FIG. 9 shows a metallization process that uses conventional techniques to deposit a metallization layer 46 over the entire surface of HBT 20.

[0046] FIG. 10 illustrates a tenth processing stage that follows the ninth processing stage depicted in FIG. 9. FIG. 10 shows yet another patterning and etching process. Conventional photolithographic techniques can be used to pattern HBT 20, and then etching is performed to remove metallization layer 46 where not wanted over the surface of HBT 20. However, metallization layer 46 remains within and over vias 44 to form electrical contacts with the base, collector, and emitter regions of HBT 20.

[0047] FIG. 11 shows a schematic, zero biased, band diagram for HBT 20. FIG. 11 depicts a conduction band (Ec) trace 48 and a valence band trace (Ev) 50 on vertically opposing sides of a Fermi level (Ef) 52. The band diagram of FIG. 11 is horizontally partitioned into four sections 30′, 34′, 36′, and 40′ corresponding to collector region 30, base region 34, first emitter layer 36, and second emitter layer 40 (FIG. 10), respectively.

[0048] Referring to FIGS. 10-11, in collector region 30 the bandgap energy equals Ec−Ev, or approximately 1.12 eV. In base region 34 the bandgap energy still equals approximately 1.12 eV. In other words, base region 34 has roughly the same bandgap as collector region 30.

[0049] In first emitter layer 36, the bandgap energy equals approximately 1.42 eV. This increase of roughly 0.3 eV from the bandgap of base region 34 and collector region 30 is due to the higher bandgap of GaAs compared to the bandgap of Si. Moreover, substantially all of this 0.3 eV appears as a discontinuity 54 in the valence band Ev. Very little of the increase in bandgap achieved by transitioning from Si to GaAs in first emitter layer 36 appears in conduction band Ec.

[0050] In second emitter layer 40, the bandgap equals approximately 2.24 eV. This represents an increase of roughly 0.8 eV from the bandgap in first emitter layer 36. Accordingly, another discontinuity in the bandgap energy results. This discontinuity is divided between a valence band discontinuity 56 of approximately 0.5 eV and a conduction band discontinuity 58 of approximately 0.3 eV. The total bandgap discontinuity between second emitter layer 40 and base region 36 is approximately 1.1 eV, with the majority of the discontinuity appearing in the valence band Ev. The majority of the discontinuity appearing in the valence band Ev is desirable for NPN transistors because it is the parameter that characterizes the suppression of hole injection.

[0051] Not only does first emitter layer 36 provide a stable, abrupt semiconductor junction at base region 34 and simultaneously allow second emitter layer 40 to be epitaxially grown with few defects, but first emitter layer 36 also causes a larger portion of the total bandgap discontinuity between multilayer emitter 38 and base region 34 to appear as a valence band discontinuity, which is particularly useful in suppressing hole injection. This relatively large valence band discontinuity significantly suppresses hole injection from base region 34 to multilayer emitter 38, creating an HBT with greatly improved emitter injection efficiency compared to prior art HBTs.

[0052] FIGS. 12-21 show sectional views of an HBT 60 at first through tenth processing stages, respectively. HBT 60 is an alternative embodiment to HBT 20, discussed above. In general, HBT 60 is an upside down implementation of HBT 20, with an emitter region of the GaP layer being the bottom-most portion of the intrinsic transistor and being surrounded by a GaP region that is configured to be substantially insulative. HBT 60 operates substantially in accordance with the band diagram illustrated in FIG. 11.

[0053] FIG. 12 illustrates a first processing stage in which a non-silicon semiconductor layer 62, preferably gallium arsenide (GaAs) is epitaxially grown over and in contact with a silicon (Si) substrate 64, and another non-silicon semiconductor layer 66, preferably gallium phosphide (GaP) is then epitaxially grown over and in contact with layer 62. Preferably, substrate 64 is undoped and left to exhibit its intrinsic doping so that it will exhibit low conductivity for improved radiation tolerance and reduced capacitance with the intrinsic transistor, discussed below.

[0054] As with first emitter layer 36, discussed above in connection with the first embodiment, layer 62 is limited in thickness so that it will be coherently strained between Si substrate 64 and layer 66. With layer 62 made from GaAs, a thickness of less than 200 Å is preferred, with a thickness of less than 50 Å being particularly desirable. Layer 62 is extrinsic to HBT 60 and serves primarily as a buffer between Si substrate 64 and the above-layer. However, layer 62 also substantially prevents interdiffusion at the boundary between substrate 64 and layer 62, and the formation of a conductive region due to any interdiffusion.

[0055] In an alternative embodiment (not shown), layer 62 may be omitted, and layer 66 grown to a greater thickness than would be needed when layer 62 is included. In this embodiment, defects are likely to form in layer 66 near substrate 64, but such defects are minimized as layer 66 becomes thicker.

[0056] Layer 66 is preferably a wide bandgap semiconductor that exhibits or can be selectively made to exhibit good insulative qualities and exhibits good or can be made to exhibit good thermal conductivity qualities. Preferably, GaP is used for layer 66. Desirably, layer 66 is grown to a large thickness, preferably greater than 5000 Å when layer 62 is present, but this is not a requirement of the present invention. Standard techniques, as discussed above in connection with the first embodiment, may be used to grow layer 66.

[0057] As indicated by a dotted line in FIG. 12, layer 66 is divided into an undoped region 68 and a doped region 70. In undoped region 68, layer 66 is desirably formed to exhibit insulative properties, such as the insulative properties demonstrated by GaP that exhibits only its intrinsic doping [GaP(i)]. In doped region 70, layer 66 is desirably doped to exhibit “N” type doping [GaP(n)] in this NPN example. Doping may be accomplished by adding a suitable dopant while growing doped region 70 of layer 66. Layer 66 exhibits increased conductivity in doped region 70 due to the doping.

[0058] In this embodiment, doped region 70 will provide an outside layer, which also serves as a penultimate inside layer, of a multilayer emitter 72 for HBT 60. Accordingly, doped region 70 is intrinsic to HBT 60, but undoped region 68 is extrinsic to HBT 60 because it does not take a substantial part in the electrical activity of HBT 60. The function of doped region 70 is similar to that of second emitter layer 40, discussed above in connection with the first embodiment.

[0059] The depth of doped region 70 in layer 66 desirably varies to achieve application goals. Generally, a high-speed transistor will benefit from doped region 70 being relatively shallow so that emitter resistivity is raised and base-emitter junction capacitance is lowered. Moreover, a greater thickness for insulative, undoped region 68 is desirable because it decreases capacitance with layers underlying the intrinsic transistor and improves radiation tolerance.

[0060] FIG. 13 illustrates a second processing stage that follows the first processing stage depicted in FIG. 12. In this second stage, a third non-silicon, semiconductor layer 74 is grown over and in contact with layer 66. Layer 74 has a function similar to that of layer 36, discussed above. In particular, layer 74 provides an interdiffusion barrier between layer 66 and subsequent Si layers, discussed below, and layer 74 buffers between the different materials used for layer 66 in the subsequent Si layers. Layer 74 is desirably formed substantially of GaAs.

[0061] Layer 74 is limited in thickness so that layer 74 will be coherently strained between layer 66 and subsequent Si layers. With layer 74 made from GaAs and layer 66 made from GaP, a thickness for layer 74 of less than 200 Å is preferred, with a thickness of less than 50 Å being more desirable. Layer 74 may be lightly N-type doped for this NPN implementation or may exhibit its intrinsic doping, but is preferably configured not to intentionally exhibit P-type conductivity. Layer 74 provides an inside layer, which also serves as a penultimate outside layer, of multilayer emitter 72 for HBT 60, and is therefore an intrinsic part of HBT 60.

[0062] FIG. 14 illustrates a third processing stage that follows the second processing stage depicted in FIG. 13. In this third stage, a Si layer 76 is epitaxially grown over and in contact with layer 74. In accordance with conventional processing techniques, layer 76 may be grown in a chamber separate from the chamber used to grow layers 62, 66, and 74 to minimize the risk of chamber contamination. In order to move the wafer to a new chamber, a thin (e.g., 50 Å) Si layer (not shown) may be temporarily grown on layer 74 to protect the exposed surface of layer 74, then this temporary layer removed through etching when the wafer has been moved into the new chamber.

[0063] Layer 76 is preferably grown to exhibit three regions of differing conductivity type. A region 78, which will serve as the base of HBT 60, is grown over and in contact with layer 74. The boundary between layer 74 and base region 78 will serve as the base-emitter junction for HBT 60. Since layers 66 and 74 are non-silicon layers and base 78 is a silicon layer, a heterojunction results.

[0064] Si layer 76 and subsequent processing stages are desirably grown while keeping temperatures below 800° C. to preserve an abrupt base-emitter junction. Base 78 is heavily doped to exhibit P-type conductivity [Si(p+)] for this NPN implementation by adding a suitable dopant while growing base 78 of layer 66. Desirably, base 78 is heavily doped so that the base of HBT 60 will exhibit an unusually low resistance. A small amount of Ge may be mixed with the Si of base 78 to lower the bandgap of the base of HBT 60 when compared to the bandgap of a base formed using more pure Si. Desirably, base 78 is grown to a thickness greater than 1000 Å, with a thinner base 78 being more desirable for higher speed characteristics.

[0065] Si layer 76 is grown to include a collector region 80 over and in contact with base 78. Collector 80 may be grown to a thickness of greater than 2000 Å, with less thickness being more desirable in lower voltage applications. As a minimum, layer 76 needs to be sufficiently thick so that subsequent metallization does not diffuse through collector 80 to short with base 78. Collector 80 is lightly doped to exhibit N-type conductivity [Si(n−)] for this NPN implementation by adding a suitable dopant while growing collector 80.

[0066] Si layer 76 is also grown to include a collector-contact-enabling region 82 over and in contact with collector region 80. Region 82 may have a thickness in the range of 1000-4000 Å. Region 82 differs from region 80 in that region 82 is highly doped [Si(n+)] to enable an interface with a metal contact, to be applied later. Regions 80 and 82 will be collectively referred to below simply as collector 80.

[0067] FIG. 15 illustrates a fourth processing stage that follows the third processing stage depicted in FIG. 14. FIG. 15 shows a patterning and etching process. Conventional photolithographic techniques can be used to pattern HBT 60, then etching is performed to remove a portion of regions 82 and 80 from Si layer 76 so that only the feature that will be used as collector 80 for HBT 60 remains. Desirably, etching is stopped below heavily doped contact-enabling region 82 and somewhere in the middle of the lightly doped region 80. The precise location for stopping the etching process is not a critical parameter. FIG. 15 illustrates HBT 60 following the removal of a mask used in this etching process. Collector 80 will be centrally located in HBT 60.

[0068] FIG. 16 illustrates a fifth processing stage that follows the fourth processing stage depicted in FIG. 15. FIG. 16 shows a masking and ion implantation process. Conventional photolithographic and etching techniques can be used to pattern and etch HBT 60 to form a suitable mask 84 (e.g., Si3N4), then ion implantation is performed in base-contact-enabling areas 86. Implantation energies are adjusted to that a highly conductive P-type dopant (p+) for this NPN example is driven through the remaining portion of lightly doped Si(n−) region 80 into, but not through, base 78 at base-contact-enabling areas 86. The highly conductive p+ dopant overwhelms the lightly conductive n− dopant to result in areas 86 being Si(p+). Implantation may occur in two steps, with a higher energy implantation step followed by a lower energy implantation step. The higher energy step causes the dopant to be driven to a large depth and the lower energy step causes the dopant to be driven only to a small depth so that base-contact-enabling areas 86 are continuous Si(p+) regions from the exposed surface down into base 78.

[0069] FIG. 17 illustrates a sixth processing stage that follows the fifth processing stage depicted in FIG. 16. Compared to the fifth processing stage of FIG. 16, mask 84 is removed, and conventional photolithographic and etching techniques have been performed to remove remaining portions of Si layers 78 and 80 not needed for base 78 or collector 80. The removed portions are outside of base-contact-enabling areas 86. The remaining portion of layer 76 forms base 78 and collector 80. After this patterning and etching step, a masking and ion implantation process is performed to apply a suitable mask 88 (e.g., Si3N4) which has openings in emitter-contact-enabling areas 90. When mask 88 has been applied, ion implantation is performed in emitter-contact-enabling areas 90 by driving a suitable highly conductive n+ dopant for this NPN example through GaAs layer 74 into doped region 70 of GaP layer 66.

[0070] FIG. 18 illustrates a seventh processing stage that follows the sixth processing stage depicted in FIG. 17. FIG. 18 shows isolation, passivation and metallization processes. In particular, FIG. 18 depicts etching of an isolation well 92, the application of a passivation layer 94, and then the application of a metallization layer 96.

[0071] First, a suitable mask is applied (not shown) and well 92 etched around the perimeter of HBT 60 to isolate HBT 60 from other transistors and devices (not shown) formed over substrate 64. Well 92 is etched into insulative (undoped) region 68 in layer 66, or deeper, for effective isolation. While the area surrounded by well 92 is not a critical parameter of the present invention, a smaller area is desirable for higher transistor density and faster performance.

[0072] Next, conventional techniques are used to apply passivation layer 94 over the entire surface of HBT 60 at this point. Silicon nitride, silicon dioxide, or other conventional passivation materials may be applied in a conventional manner, so long as temperatures generally remain below about 800° C. Then, a patterning and etching process is performed in which conventional techniques may be used to pattern HBT 60 and remove selected portions of passivation layer 94 to form vias in locations where metallization layer 96 will eventually make electrical contacts with the emitter, base, and collector of HBT 60.

[0073] Finally, conventional techniques may be used to deposit metallization layer 96 over the entire surface of HBT 60. After deposition of metallization layer 96, another patterning and etching process removes metallization layer 96 where not wanted over the surface of HBT 60. However, metallization layer 96 remains within and over the above-discussed vias to form an emitter contact 98 at emitter-contact-enabling areas 90, a base contact 100 at base-contact-enabling areas 86, and a collector contact 102 at collector 80. Collector contact 102 is centrally located (i.e., innermost) within HBT 60. Base contact 100 is intermediately located within HBT 60 and may substantially surround collector contact 102. Emitter contact 98 is peripherally located (i.e., outermost) within HBT 60 and may substantially surround base contact 100 and collector contact 102. In addition, the pattern of metallization is configured so that metallization layer 96 is routed to other circuits and/or pads to make HBT 60 usable in an electrical circuit.

[0074] Due to the thin, coherently strained nature of emitter layer 74, multilayer emitter 72 and base 78 exhibit few defects. Moreover, multilayer emitter 72 provides a clean, abrupt semiconductor junction at base layer 78, and allows base 78 and collector 80 to be epitaxially grown to a relatively thick width with few defects. The band diagram depicted in FIG. 11 applies for HBT 60 as discussed above for HBT 20.

[0075] Referring to FIGS. 10 and 18, HBT 60 (FIG. 18) is upside down relative to HBT 20 (FIG. 10). In both HBT 20 and HBT 60 a multilayer, non-silicon emitter forms a base-emitter junction with a Si base, and the collector, base, and emitter are arranged vertically. The emitter is on the top in HBT 20 (i.e., distally located relative to substrate 24), but on the bottom in HBT 60 (i.e., proximally located relative to substrate 64). In the preferred embodiments, GaP is used for the outermost emitter layer that is intrinsic to HBTs 20 and 60.

[0076] In HBT 60 (FIG. 18), the intrinsic portion of GaP layer 66 is confined to doped region 70. However, doped region 70, and the other features that are intrinsic to HBT 60, are spaced apart from substrate 64 and from other HBTs 60 (not shown) which may be formed over the same substrate 64 by undoped region 68 of GaP layer 66. In the preferred embodiments, undoped region 68 exhibits the good insulative properties and good thermal conductivity properties characteristic of undoped GaP. Accordingly, the insulative properties promote lower parasitic capacitance and improved speed along with less electron disturbance in the presence of radiation and improved radiation tolerance. The good thermal conductivity properties allow heat generated by the intrinsic portions of HBT 60 to be readily conducted to Si substrate 64, which is also a good thermal conductor. Accordingly, a greater number of HBTs 60 may be formed on substrate 64 or higher power HBTs 60 may be formed.

[0077] In summary, an improved HBT having a wide bandgap with a low interdiffusion base-emitter junction is provided along with methods for forming the HBT. The HBT uses a Si substrate, which is desirable because the use of a Si substrate takes advantage of the existing manufacturing infrastructure that reliably produces relatively rugged Si wafers at low cost.

[0078] A multilayer emitter is provided in the HBT. This emitter exhibits a wide bandgap, and the resulting base-emiter junction is substantially free of interdiffusion. In a preferred embodiment, the HBT is provided with a Si base that forms a heterojunction with a multilayer emitter having a thin GaAs layer proximate the base and a distal GaP layer. The base-emitter junction and the wide bandgap multilayer emitter together allow an HBT configured in accordance with the present invention to exhibit performance more closely meeting theoretical expectations than does the performance of conventional HBTs. In one embodiment, the HBT uses a Si substrate and a substantially insulative crystalline layer grown thereon, with the features intrinsic to the HBT formed in and above this insulative crystalline layer.

[0079] The present invention has been described above with reference to preferred embodiments. However, those skilled in the art will recognize that changes and modifications may be made in these preferred embodiments without departing from the scope of the present invention. For example, while the above-presented description discusses the formation of a single HBT, those skilled in the art will readily recognize that a multiplicity of HBTs may be simultaneously formed as described above, or in an equivalent manner, for integrated circuit or discrete transistor applications. These and other changes and modifications that are obvious to those skilled in the art are intended to be included within the scope of the present invention.

Claims

1. A vertical heterojunction bipolar transistor comprising: a gallium phosphide layer (GaP) configured to exhibit a first conductivity type, said GaP layer forming a first portion of a multilayer emitter; a gallium arsenide (GaAs) layer formed in contact with said GaP layer, said GaAs layer forming a second portion of said multilayer emitter; a silicon (Si) base region of a second conductivity type formed in contact with said GaAs layer; and a Si collector region of said first conductivity type formed adjacent to said Si base region.

2. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein said GaAs layer is less than 200 Å thick.

3. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein said GaAs layer is sufficiently thin so as to be coherently strained.

4. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein said GaAs layer is configured so as not to exhibit said second conductivity type.

5. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein a base-emitter transistor junction located at an interface between said Si base region and said GaAs layer is substantially free of interdiffusion.

6. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein said GaAs layer and said GaP layer are epitaxially grown.

7. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein said transistor additionally comprises a Si substrate positioned underneath said GaP layer.

8. A vertical heterojunction bipolar transistor as claimed in claim 7 wherein said GaAs layer is a first GaAs layer and said transistor additionally comprises a second GaAs layer between said Si substrate and said GaP layer.

9. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein: said GaP layer is configured to have a first region doped to exhibit said first conductivity type, said first region of said GaP layer being in contact with said GaAs layer and forming said first portion of said multilayer emitter; and said GaP layer is configured to have a second region in contact with said second GaAs layer, said second region being substantially undoped.

10. A vertical heterojunction bipolar transistor as claimed in claim 9 wherein said first GaP region is intrinsic to said heterojunction bipolar transistor and said second GaP layer is extrinsic to said heterojunction bipolar transistor.

11. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein: said GaP layer is configured to have a first region doped to exhibit said first conductivity type, said first region of said GaP layer being in contact with said GaAs layer and forming said first portion of said multilayer emitter; and said GaP layer is configured to have a second region in contact with said second GaAs layer, said second region being substantially insulative.

12. A vertical heterojunction bipolar transistor as claimed in claim 1 wherein: said GaAs layer is formed over said GaP layer; said Si base region is formed over said GaAs layer; and said Si collector region is formed over said Si base region.

13. A vertical heterojunction bipolar transistor as claimed in claim 1 additionally comprising an emitter contact coupled to one of said GaAs layer and said GaP layer, a base contact coupled to said Si base region, and a collector contact coupled to said Si collector region, wherein said emitter contact is an outermost one of said emitter, base, and collector contacts, and said collector contact in an innermost one of said emitter, base, and collector contacts.

14. A vertical heterojunction bipolar transistor comprising: a first non-silicon layer exhibiting a first conductivity type and a bandgap wider than silicon, said first non-silicon layer forming a first layer of a multilayer emitter; a second non-silicon layer in contact with said first non-silicon layer, said second non-silicon layer forming a second layer of said multilayer emitter; a silicon (Si) base layer of a second conductivity type formed in contact with said second non-silicon layer, wherein an base-emitter transistor junction is formed at a boundary between said second non-silicon layer and said base layer and wherein said base-emitter transistor junction is substantially free of interdiffusion; and a Si collector of said first conductivity type formed adjacent to said base layer.

15. A vertical heterojunction bipolar transistor as claimed in claim 14 wherein: said first non-silicon layer is configured to have a first region doped to exhibit said first conductivity type, said first region being intrinsic to said heterojunction bipolar transistor; and said first non-silicon layer is configured to have a second region which is substantially insulative, said second region being extrinsic to said heterojunction bipolar transistor.

16. A vertical heterojunction bipolar transistor as claimed in claim 14 wherein said second non-silicon layer is gallium arsenide (GaAs).

17. A vertical heterojunction bipolar transistor as claimed in claim 14 wherein said second non-silicon layer is coherently strained between said silicon base layer and said first non-silicon layer.

18. A vertical heterojunction bipolar transistor as claimed in claim 17 wherein said second non-silicon layer is gallium arsenide (GaAs) and has a thickness of less than 200 Å.

19. A vertical heterojunction bipolar transistor as claimed in claim 14 wherein said first non-silicon layer is gallium phosphide (GaP).

20. A vertical heterojunction bipolar transistor as claimed in claim 14 wherein said transistor additionally comprises a Si substrate, wherein said first non-silicon layer is formed over said Si substrate.

21. A vertical heterojunction bipolar transistor as claimed in claim 20 wherein: said first non-silicon layer is formed substantially of gallium phosphide (GaP); said first non-silicon layer is configured to have a first region doped to exhibit said first conductivity type, said first region being in contact with said second non-silicon layer; and said first non-silicon layer is configured to have a second region proximate said Si substrate, said second region not being doped to exhibit said first conductivity type.