1. Field of the Invention
This invention relates to semiconductor fabrication, and particularly to forming a vertical profile FinFET gate having metallic spacers formed via plating surfaces of a thin gate dielectric exposed by a patterned mask.
2. Description of Background
Integrated circuits often employ active devices known as transistors such as field effect transistors (FET's). A current integrated circuit FET includes a silicon-based substrate comprising a pair of impurity regions, i.e., source and drain junctions, spaced apart by a channel region. A gate electrode is dielectrically spaced above the channel region of the silicon-based substrate. The junctions can comprise dopants which are opposite in type to the dopants residing within the channel region interposed between the junctions. An interlevel dielectric can be disposed across the FET's of an integrated circuit to isolate the gate areas and the junctions from interconnect lines which overlie the FET's. Ohmic contacts can be formed through the interlevel dielectric to the gate areas and/or junctions to couple them to the overlying interconnect lines.
There are ongoing efforts to reduce the size of FET's to meet the high demand for increased device performance and increased circuit density. However, reducing the size of FET's undesirably increases the cost and difficulty of manufacturing those devices. A special type of FET known as a “finFET” has been developed as a type of device that will enable continuing FET size reduction and increased device performance. The body of a finFET is formed from a structure referred to as a “fin”, which extends vertically above the silicon-based substrate. The source and drain junctions are formed in the fin. The gate electrode of a finFET is formed across a central channel region of the fin and adjacent to one or more sides of the fin. The formation of the gate electrode can entail depositing a conductive layer across the fin and the substrate, patterning a photoresist mask using photolithography across the conductive layer, and etching (e.g., reactive ion etching (RIE)) regions of the conductive layer not protected by the mask to define the gate electrode.
Unfortunately, the overall resolution of the photolithography process used to form the gate electrodes of finFET's is limited. This overall resolution depends on parameters such as the properties of the photoresist and the resolution of the optical lithography system, i.e., the ability to form a resolvable image pattern on the semiconductor topography. Also, problems with the etch technique can occur. For example, the highly anisotropic nature of RIE can compromise its selectivity and can damage the surface of the material being etched. These limitations of the photolithography and etching processes can be exacerbated as the density of the finFET's is increased. As a result, the finFET gates are very difficult to form in accordance with design specifications.
The shortcomings of the prior art are overcome and additional advantages are provided through the provision of vertical profile finFET gates formed via plating upon a thin gate dielectric. In an embodiment, a method for forming a transistor comprises: providing a semiconductor substrate, and a semiconductor fin structure extending above the substrate; forming a gate dielectric across exposed surfaces of the semiconductor topography; patterning a mask upon the semiconductor topography such that only a select portion of the gate dielectric is exposed that defines where a gate electrode is to be formed; and plating a metallic material upon the select portion of the gate dielectric to form a gate electrode across a portion of the fin structure.
In one embodiment, a transistor comprises: a semiconductor fin structure extending above a semiconductor substrate and comprising source and drain junctions; and a plated gate electrode extending across a portion of the fin structure, the gate electrode being in direct contact with a gate dielectric interposed between the gate electrode and the fin structure.
In another embodiment, a pair of transistors comprises: a pair of semiconductor fin structures spaced apart above a semiconductor substrate, each fin structure comprising source and drain junctions; and a single plated gate electrode extending across and between portions of the fin structures, the gate electrode being in direct contact with a gate dielectric interposed between the gate electrode and the fin structures.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
b), 6(b), 7(b), 8(b), and 9(b) depict top plan views taken through mid-sections of the semiconductor topographies depicted in
The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
Methods are described for forming a finFET by plating a gate electrode upon surfaces of a gate dielectric exposed by a patterned mask. The method described herein avoids the problems associated with lithographically patterning and etching the finFET gate electrode. For example, due to the relatively low selectivity of RIE, long etch times can be required to perform RIE patterning of the gate electrode, which can undesirably introduce unacceptable linewidth variations to the gate electrode. Plating the gate electrode instead of etching it can provide for the formation of a very uniform gate electrode having a highly vertical profile.
b) illustrate an exemplary embodiment of a method for forming dual finFET's comprising a single gate electrode. Dual finFET's can be employed for applications such as inverters or where multiple fins are gated in parallel to carry additional current. It is understood that a single finFET comprising a single gate electrode or a plurality of finFET's could alternatively be formed in a similar manner. First, as depicted in
Turning to
As illustrated in
A metallic material can be electroplated “through” the exposed surfaces of the gate dielectric 20 such that the slot 24 in the mask 22 is filled. The plating can be performed for a period of time sufficient to fill small spaces and to allow the metallic material to meet across spaces between adjacent fins to form continuous lines. As used herein, “metallic” refers to any material comprising metal including pure metals and alloys of metals. Examples of suitable metallic materials include, but are not limited to, Al, Co, Cr, Fe, Ir, Hf, Mg, Mo, Mn, Ni, Pd, Pt, La, Os, Nb, Rh, Re, Ru, Sn, Ta, Ti, V, W, Y, Zr, and alloys of the foregoing metals.
The electroplating can be performed by immersing the semiconductor topography shown in
After the electroplating process is terminated by removing the semiconductor topography from the plating bath and rinsing it with water, the mask 22 can be stripped to reveal the gate electrode 26 shown in
Turning to
Subsequent to forming the LPD oxide layer 28, the electroplating process can be repeated to plate additional metallic material 30 upon the surfaces of the gate electrode 26, as depicted in
Source/drain junctions that are self-aligned to the sidewall surfaces of the metallic material 30 (i.e., the spacers) can subsequently be implanted into the semiconductor fin structures 12 to complete the formation of the finFET devices. In the case of NFET's, the source/drain junctions can be implanted with n-type dopants, whereas in the case PFET's, the source/drain junctions can be implanted with p-type dopants. Examples of n-type dopants include, but are not limited to, arsenic and phosphorus, and an example of a p-type dopant includes, but is not limited to, boron. It is to be understood that both NFET and PFET devices can be formed within different fin structures 12 to form a CMOS (complementary metal-oxide semiconductor) circuit. Contacts also can be formed to the gate electrode 26 coated with metallic material 30, and to the source/drain junctions (i.e., the fin structures 12) to electrically contact the finFET transistors to overlying interconnect levels of the integrated circuit.
As used herein, the terms “a” and “an” do not denote a limitation of quantity but rather denote the presence of at least one of the referenced items. Moreover, ranges directed to the same component or property are inclusive of the endpoints given for those ranges (e.g., “about 5 wt % to about 20 wt %,” is inclusive of the endpoints and all intermediate values of the range of about 5 wt % to about 20 wt %). Reference throughout the specification to “one embodiment”, “another embodiment”, “an embodiment”, and so forth means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the embodiment is included in at least one embodiment described herein, and might or might not be present in other embodiments. In addition, it is to be understood that the described elements may be combined in any suitable manner in the various embodiments. Unless defined otherwise, technical and scientific terms used herein have the same meaning as is commonly understood by one of skill in the art to which this invention belongs.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.