Claims
- 1. A method for fabricating an integrated circuit structure, said method comprising the steps of:
cutting a substrate along a higher order crystal orientation, thus exposing the higher order crystal orientation; and fabricating at least one each of PMOS and NMOS vertical transistors on the exposed higher order crystal orientation of said substrate.
- 2. A method as in claim 1, wherein said higher order orientation is selected from the group consisting of (111), (311), and (511) crystal orientations.
- 3. A method as in claim 1, wherein said vertical transistors are formed so as to easily go into velocity saturation due to increased hole mobility.
- 4. A method as in claim 1, wherein said PMOS and NMOS transistors are fabricated as deep sub-micron devices.
- 5. A method as in claim 1, wherein said substrate is a silicon substrate.
- 6. A method as in claim 1, wherein said substrate is silicon on an insulator.
- 7. An integrated circuit structure, comprising:
a silicon substrate having a higher order crystal plane; and NMOS and PMOS transistors formed vertically on said higher order crystal plane of said silicon substrate.
- 8. An integrated circuit structure as in claim 7, wherein said higher order crystal plane is selected from the group consisting of (111), (311), and (511) crystal planes.
- 9. A processor-based system comprising:
a processor; a memory device coupled to said processor, said memory device comprising at least one memory circuit, said memory circuit comprising:
a substrate having a higher order crystal orientation; and at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair fabricated on said higher order crystal orientation; and a storage device coupled to said CMOS transistor pair.
- 10. A processor-based system as in claim 9, wherein said memory device is a one of an SRAM and a DRAM.
- 11. A processor-based system as in claim 9, wherein said processor-based system is a computer system.
- 12. A method of operating a CMOS circuit comprising:
providing an integrated circuit having PMOS and NMOS transistors fabricated in a higher order surface of a silicon wafer; and biasing said transistors to operate in velocity saturation.
- 13. A method of operating a CMOS circuit as in claim 12, wherein said higher order surface is one of the (111), (311), (511) or yet higher order surfaces.
- 14. A memory circuit comprising:
at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair on a higher order surface of a silicon substrate.
- 15. A memory circuit as in claim 14, wherein said higher order surface is one of the (111), (311), (511) or yet higher order surfaces.
- 16. A memory circuit as in claim 14, wherein said NMOS and PMOS transistors have matching characteristics.
- 17. A memory circuit as in claim 15, wherein said memory circuit is a DRAM memory circuit.
- 18. A memory circuit as in claim 15, wherein said memory circuit is an SRAM memory circuit.
- 19. A processor-based system comprising:
a processor; a memory device coupled to said processor, said memory device comprising at least one memory circuit, said memory circuit comprising:
a substrate having a higher order crystal orientation; and at least one pair of NMOS and PMOS transistors formed as a CMOS transistor pair fabricated on said higher order crystal orientation; and a storage device coupled to said CMOS transistor pair.
- 20. A processor-based system as in claim 19, wherein said higher order crystal orientation is selected from the group consisting of (111), (311), (511) and still higher order surface orientations.
- 21. A processor-based system as in claim 20, wherein said memory device is one of a DRAM and an SRAM.
- 22. A processor-based system as in claim 21, wherein said processor-based system is a computer system.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is related to Application No. ______ filed on even date herewith and entitled METHOD FOR FABRICATING CMOS TRANSISTORS HAVING MATCHING CHARACTERISTICS AND APPARATUS FORMED THEREBY (Attorney Docket No. M4065.0204), the contents of which are incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09386313 |
Aug 1999 |
US |
Child |
10222997 |
Aug 2002 |
US |