Patent Application
20070236895
The present invention relates generally to the data processing field, and more particularly, relates to a method and via resistor structure for implementing a resistor and for trimming a resistance value of the resistor.
With the advent of generally standard signaling schemes popular with processor-to-processor structures, such as, Front-side-busses, memory interfaces, and the like, the application of resistors as pull-ups, bias networks, series damping networks, and the like, has become very popular. Physical standards such as Gunning Transistor Logic (GTL) require resistors as part of their structure. These resistors have been growing in numbers on a typical electronic part for years, and with wider and more prevalent high speed busses, are increasing in numbers drastically.
Approaches being employed today range from smaller devices, to resistor packs, to embedding resistors on ASICS, to placing expensive resistive layers in the card stackup, to other approaches such as described in U.S. Pat. No. 6,404,643.
U.S. Pat. No. 6,404,643 shows a complicated set of steps to place a component within a cavity of a board, and overmold the component in such a way to make the component an integral part of the card/board structure. The disclosed arrangement is not very space efficient, and not likely to be high yielding given the process steps described.
U.S. Pat. No. 5,990,421 discloses a printed circuit board having a layer of electrically resistive material that can provide a pull-up/pull-down resistor for the printed circuit board. The printed circuit board includes a substrate which has a conductive plane located on the top surface of the board. The conductive plane is typically dedicated to electrical power. The board also has a via that is connected to an internal signal line. The resistive material is applied to the top surface to connect the conductive plane to the via and the signal line. The resistive material can be applied with a screening process, which simplifies the assembly process of the resistor. Additionally, the resistive material is relatively small and located adjacent to the via so that the resistor does not occupy valuable board space. The resistor is always present and a series damping resistor is not enabled, and there is no adjustment capability for the pull-up or pull-down resistor. The top plane being ground or power, the resistor defined by a circular pad on the top of the card is connected between the via and the power plane structure, which is required to be on the outside of the card.
The above-described patents do not address split terminations, series terminations or the ability to adjust a resistor value from negligible to several orders of magnitude larger than its un-trimmed value.
In order to save space, for example, for a given number of resistors that may be required, a method of combining the resistor with a structure, which already exists on the card, is needed. A method to adjust the value of the resistor also is needed to trim the resistor to a desired value that allows for significant variation of the resistance value without adding significant inductance or capacitance to the via. Being able to define the presence or absence of a resistor or a value of the resistor in a net post design, for example, a damping resistor in a net, would be very beneficial in adjusting memory net performance for the wide range of memory driver and receiver behaviors.
Principal objects of the present invention are to provide a method and a via resistor structure for implementing a resistor and for trimming a resistance value of such resistor. Other important aspects of the present invention are to provide such method and structure substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a via resistor structure and method are provided for implementing a resistor and for trimming a resistance value of the resistor. A resistive material selectively is deposited adjacent to a pad connecting to a via where a resistor is to be defined. A trimmed path is formed in the resistive material for selectively changing the resistance value of the resistor.
In accordance with features of the invention, the resistive material is implemented with a selected one of an e-coat material being loaded with at least one of a selected metal and a particulate, a plated graphite, and a polymer thick film.
In accordance with features of the invention, laser cutting forms the trimmed path in the resistive material, such as a spiral-trimmed path. A longer cut increases the resistance value of the resistor.
In accordance with features of the invention, the via resistor structure enables series damping resistors, pull-up and pull-down resistors, and split terminations.
The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
In accordance with features of the invention, a space saving arrangement for a given number of resistors is provided by combining a resistor with a via structure, which already exists on a printed circuit card. A method to adjust the value of the resistor also is provided to trim the resistor to a desired value and that allows for significant variation of the resistance value without adding significant inductance or capacitance to the via. The method enables defining the presence or absence of a resistor or a value of the resistor in a net post design. For example, a damping resistor in a net advantageously is provided by the method of the invention that is very beneficial in adjusting memory net performance for the wide range of memory driver and receiver behaviors.
In accordance with features of the invention, a tuneable via resistor structure is provided utilizing a spiral trimming process, which can be manufactured in an efficient plating process and invoked for pull-up and pull-down resistors, split terminations, and series damping resistors. This resistor can be selectively present or absent, or can be placed in a blanket, for example, on selected via caps or all via caps, and trimmed to a needed value.
In accordance with features of the invention, by utilizing a via and a pad connecting to the via, to construct the resistor, a smaller, more dense, more versatile, and more accessible resistor structure advantageously is provided relative to current approaches including resistive layer techniques. This accessibility allows for tuning or changing of the resistance value post raw-card manufacturing, providing an option for in situ tuning of the resistance value, such as for tuned net situations.
Having reference now to the drawings, in
Via resistor structure 100 includes a resistive material generally designated by the reference character 104. A spiral trimmed path generally designated by the reference character 106 is formed in the resistive material 104 for tuning or changing of the resistance value of the resistor 102 defined by resistive material 104. It should be understood that the present invention is not limited to such spiral-trimmed path 106; various other path configurations can be used.
The resistive material 104 includes for example, an e-coat material, such as including an epoxy material, a urethane material or other adhesive material, loaded with a selected one of various metals, particulates, or the like to tailor a specific resistivity characteristic. Other exemplary materials that could be used for the resistive material 104 include, for example, plated graphite and various screened polymer thick films.
In accordance with features of the invention, a methodology to be used includes starting with a base line via resistor structure with no trim cut and measure the resistance, inductance, and capacitance (R/L/C) properties of the via resistor structure 100 followed by a long spiral cut 106 and another measurement of the resulting R/L/C properties of the via resistor structure 100. A significant desired effect that is achieved with the via resistor structure 100 of the invention is that a selected adjustment of the resistance value is enabled, that can include a generally large change in the resistance value with little change in capacitance and inductance, using the trim cut in the deposited resistive material, such as the spiral trimmed path 106 as shown in
Via resistor structure 100 includes an exemplary elongated, electrically conductive via generally designated by the reference character 108. Electrically conductive via 108 includes an upper electrically connected conductive capture pad 110 and a lower electrically connected conductive capture pad 112. These conductive capture pads 110, 112 may or may not have a hole in the center of them depending on a particular technology medium in which this device is implemented within. An upper signal trace 114 is electrically connected to the upper resistor 102 including an annular ring serving as a mating portion 116 surrounding the resistive material 104 that defines upper resistor 102. A lower signal trace 118 similarly includes a similar annular ring serving as a mating portion 120 electrically connected to the lower resistor 102. As shown in
Via resistor structure 100 is shown in simplified form sufficient for understanding the present invention. For example, a printed circuit board (not shown) formed by an electrically insulative member typically contains a predefined pattern of a plurality of often closely spaced vias 108.
Using an available modeling tool, via structures have been constructed and solved to determine the effect of spiral cutting on these via resistors. The resistive material 104 selected in this case was E-Coat having 10000 Siemens/Meter.
The following Table 1 shows the results of the simulations:
Accounting for a power or ground plane as the first layer below the spiral cut resistor 102 would reduce the inductance impact, while not affecting the range of resistor trim capability. Further the range of trimming advantageously is enhanced with providing more spirals within the trimmed path 106.
Resistor 200 includes a spiral trimmed resistive path 204 for implementing for trimming a resistance value in accordance with the preferred embodiment. Using the test structure modeling tool for resistor 200 with the first trim path 204, a three-dimensional resistive path analysis yielded an effective resistance of about 3.5 Ohms.
Resistor 300 includes a spiral trimmed resistive path 304 having a greater length for implementing an increased resistance value for the resistor 300 as compared to resistor 200 in accordance with the preferred embodiment.
Resistor 400 includes a spiral trimmed resistive path 404 for trimming a resistance value in accordance with the preferred embodiment. For example, resistor 400 with the substantially longer trim path 404, has an effective resistance of about 73 Ohms.
In the preferred implementation of the invention, laser cutting is used for forming the trimmed resistive path. Etching could work to some degree to increase the resistance value of a resistor; however, etching would likely be difficult to align and control, and generally would not lend itself to the level of tolerance possible with the preferred laser cutting to form the trimmed path in the deposited resistive material. Other approaches such as electron-beam, plasma etch, water-jet, abrasive etching, and the like could be used to some level of tolerance and control.
While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
