Patent Application
20080054970
The foregoing features of the invention will be more readily understood by reference to the following detailed description, taken with reference to the accompanying drawings, in which:
Definitions. As used in this description and the accompanying claims, the following terms shall have the meanings indicated, unless the context otherwise requires: the term “voltage conveyor” and “buffer” shall refer to any device having an associated slew rate that includes an input for receiving a voltage and produces a voltage at an output. The term “voltage signal generator” means an electrical device that is capable of providing at its output a voltage of a predetermined value. The term “controllably coupled” shall refer to the ability to selectively couple a device to an electronic circuit by providing a control signal. The term “voltage source” refers to an electrical device that produces a voltage.
Embodiments of the invention teach integrating a low voltage circuit and a high voltage circuit on the same integrated circuit. Such an integrated circuit may be used in automatic test equipment (ATE) for testing devices, such as flash memory that include a high voltage pin that changes the mode of operation of the device under test (DUT). Although the disclosure often references ATE for its examples, the system and methodology may be employed when a controlled voltage transition is desired between a plurality of voltage states.
The pin electronics circuit 100 may include one or more of the following components: a comparator, a driver, and a load circuit (not shown). Pin electronics, as the term is understood in the art, may also include additional circuitry (not shown in
The pin electronics and the high voltage buffer are electrically connected at an output pin 140. The device under test 150 attaches to this output pin 140 by way of transmission lines (180). The integrated circuit switches between the pin electronics and the high voltage buffer by putting the output stage of the non-active circuit into a high impedance mode as indicated by 160 when the high voltage buffer is desired and placing the high voltage buffer into a high impedance mode as indicated by 170 when the low voltage pin electronics 100 are desired.
Since the voltage produced at the output pin by the high voltage buffer, PMU, or DUT can be above the supply rail voltage of the pin electronics, the supply rail voltages of the pin electronics may be adjusted upwards during high voltage operation in order to avoid destructive damage to the pin electronics which could be caused by applying high voltage signals to the low voltage (high speed) devices used to implement the pin electronics.
The supply rail voltages 310 of output stage 320 are controlled by a high voltage detector 300. The high voltage detector 300 is coupled to the output pin 140. The high voltage detector 300 responds to the voltage on the output pin 140 in such a way as to lift the supply rails 310 of the pin electronics output stage 320 up as the voltage at the output pin 140 exceeds the otherwise safe operating limit of the low voltage pin electronics output stage 320. The high voltage detector 300 can be implemented as a simple buffer whose output rises in direct proportion to the voltage at its input, but has its lower limit output excursion clamped at the default supply rail voltages of the main low voltage pin electronics circuit 330. When the voltage at output node 140 does not exceed the ordinary safe operating limit of the pin electronics output stage 320, the high voltage detector 300 maintains the supply rail voltages at the default levels. When the voltage at output node 140 exceeds the ordinary safe operating limit of the pin electronics output stage 320, the high voltage detector 300 begins to increase the supply rail voltages 310 at least proportional to the voltage at the output pin 140. As a result, the voltages of the supply rails 310 to the pin electronics are always maintained at an appropriate level to support the respective voltage at output node 140 without causing destructive damage or malfunction to output stage 320. Thus, the supply rail voltage 310 is bootstrapped by the output voltage at node 140. By bootstrapping the supply rail voltage 310 in this way, the pin electronics 100 are not damaged by the high voltages produced at output node 140 by the high voltage buffer 120, PMU or DUT (not shown).
As previously mentioned, manufacturers of integrated circuits, and more specifically flash memory require that the transition between the low voltage levels of the pin electronics and the high voltage level of the high voltage buffer be both monotonic and slew rate limited. Because of this requirement, the slew rate of the high voltage detector 300 must be at or above the slew rate of the high voltage buffer in order to avoid damage to the output stage. In order to obtain a monotonic transition, the signal must avoid both overshoot and undershoot and a single pole or overdamped response is often desired.
The circuit shown in
In the embodiment shown, there are four possible inputs: a driver voltage Va, PMU voltage Vb, a second driver voltage marked Vc, and a high voltage Vh. The circuit also includes four voltage signal generators: driver A, PMU B, other driver C, and high voltage buffer H. In addition, there are three switching elements (Sw1, Sw2, and Sw3). The switching elements are conceptual switches and may be embodied in any one of a number of ways known to those of ordinary skill in the art. For example, the switching elements may be actual complex switches, MOSFETs, or even circuitry that provides a high impedance mode in the output stage of the voltage signal generators. Sw1 switches the various input voltages to the slew limited high voltage buffer. The second switch, Sw2, connects the voltage signal generators to the DUT pin. The third switch couples the high voltage buffer to the DUT pin. Switches Sw2 and Sw3 include a high impedance voltage state Z. The high impedance voltage state Z disconnects the voltage signal generators (Z state Sw2) from the output pin or disconnects the high voltage buffer (Z state Sw3) from the output pin. Although Sw1 and Sw2 are shown as multi-pole switches, other switching mechanisms can be employed as are well known in the art. For example, each voltage signal generator may include a separate field effect transistor that acts as a switch. When all of the field effect transistors are in an off state, Sw2 is effectively in the high impedance state Z.
The circuit operates as follows. For example, if the desired change in voltage at the DUT input is between voltage level Va and voltage level Vb, Sw1 begins at position A, Sw2 begins at position A and Sw3 begins at position Z (high Z impedance state). In this initial state, node 1 is continually pre-charged to voltage level Va. Sw3 is then switched from the high impedance state, Z, to switch state D by closing the switch. Thus, the high voltage buffer is coupled to the DUT pin because the voltage at node 1 that has been pre-charged to voltage level A is equal to the voltage level at the DUT pin, the switching transient during this step will be minimized. Driver A can then be taken out of the circuit. To take driver A out of the circuit, Sw2 is switched to high impedance state Z. Thus, driver A is disconnected from the DUT, and only the high voltage buffer remains connected to the DUT. The voltage at the DUT pin has not changed as a result of node 1 being first pre-charged to a voltage substantially equal to Va.
Voltage level Vb is then connected to the input of the high voltage buffer. Sw1 switches between A and B. The voltage at the DUT gently slews at the slew rate of the high voltage buffer from voltage level Va to the voltage level Vb. The characteristic of the voltage transition from voltage level A to voltage level B is determined by the characteristic properties of the high voltage buffer. In some embodiments, voltage Va may be greater than voltage Vb; and in other embodiments, voltage Vb may be greater than voltage Va. After sufficient time has elapsed to guarantee that the voltage at the DUT pin has settled to Vb, then Sw2 is switched from Z to B, coupling the PMU driver to the DUT, which has already been charged up to a voltage substantially equal to Vb by the high voltage buffer. Sw3 is then switched from D back to the high impedance state Z. The high voltage buffer is thus disconnected from the DUT. The switches end in the states where Sw1 is switched to B, Sw2 is switched to B, and Sw3 is switched to Z. Thus, the high voltage buffer is used as a voltage conveyor allowing the voltages to transition smoothly between two states.
Similarly, the voltage conveyor can be used for transitioning between a first voltage level Va and a second high voltage level Vh wherein the second high voltage level Vh is not within the operational range of the pin electronics elements. The voltage level at the output is assumed to be at voltage level Va and the pin electronics/voltage signal generator is coupled to the output and the voltage conveyor is decoupled from the output. The voltage conveyor is then coupled to the output and receives voltage level Va at its input. The voltage signal generator is decoupled from the output and the voltage conveyor maintains the voltage at the output as voltage level Va. The voltage conveyor at its input is then controllably switched between voltage level Va and a high voltage level Vh. The voltage conveyor then causes the voltage level at the output to slew to the high voltage level Vh.
The system may include an automatic state machine, such as a control sequencer for providing control signals for controlling the switching elements.
Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made that will achieve some of the advantages of the invention without departing from the true scope of the invention. These and other obvious modifications are intended to be covered by the appended claims.
